3X endurance enhancement by advanced signal processor for 3D NAND flash memory

Lin, Weijie; Hsu, Yu-Wei; Kuo, Tsai-Hao; Yang, Y. S.; Chen, Szu-Wei; Tsao, Chun-Wei; Liu, Anchang; Ou, Lih-Yuarn; Wang, Tien-Ching; Yen, Shao-Wei; Lin, Yu-Hsiang; Lai, Kuo-Hsin; Yang, Chi-Heng; Liang, Li-Chun; Hsu, Pei-Jung

doi:10.1109/itw.2017.8278030

Cited by 5 publications

(4 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…NWI has long existed in high-density flash memory and is difficult to completely eliminate. Different from floating gate-based 2D NAND, due to changes such as 3D vertical architecture, poly-silicon channels, and charge traps, the NWI effect in 3D NAND needs further investigation [ 17 , 18 , 19 ].…”

Section: Introductionmentioning

confidence: 99%

Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors

Fan

Tian²,

Peng

et al. 2023

Sensors

View full text Add to dashboard Cite

Three-dimensional NAND flash memory is widely used in sensor systems as an advanced storage medium that ensures system stability through fast data access. However, in flash memory, as the number of cell bits increases and the process pitch keeps scaling, the data disturbance becomes more serious, especially for neighbor wordline interference (NWI), which leads to a deterioration of data storage reliability. Thus, a physical device model was constructed to investigate the NWI mechanism and evaluate critical device factors for this long-standing and intractable problem. As simulated by TCAD, the change in channel potential under read bias conditions presents good consistency with the actual NWI performance. Using this model, NWI generation can be accurately described through the combination of potential superposition and a local drain-induced barrier lowering (DIBL) effect. This suggests that a higher bitline voltage (Vbl) transmitted by the channel potential can restore the local DIBL effect, which is ever weakened by NWI. Furthermore, an adaptive Vbl countermeasure is proposed for 3D NAND memory arrays, which can significantly minimize the NWI of triple-level cells (TLC) in all state combinations. The device model and the adaptive Vbl scheme were successfully verified by TCAD and 3D NAND chip tests. This study introduces a new physical model for NWI-related problems in 3D NAND flash, while providing a feasible and promising voltage scheme as a countermeasure to optimize data reliability.

show abstract

Section: Introductionmentioning

confidence: 99%

Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors

Fan

Tian²,

Peng

et al. 2023

Sensors

View full text Add to dashboard Cite

show abstract

“…Also, severe electrostatic coupling effect causing cell-tocell interference leads to degradation of reliability. 28,29 For these reasons, it has been challenging to advance the current flash-type memory using the charge-storage operation principle.…”

Section: Introductionmentioning

confidence: 99%

Write-Once-Read-Many-Times Memory Characteristics with a Large Memory Window Operating at a Low Voltage by Li-Ion Incorporation from the LiCoO_x Ion-Supplying Layer into the InGaZnO Channel of a Thin-Film Transistor

Jeong

Han

Noh

et al. 2023

ACS Appl. Electron. Mater.

View full text Add to dashboard Cite

Write-once-read-many-times (WORM) memory characteristics with a large memory window are demonstrated in a thin-film transistor (TFT) composed of an indium-gallium-zinc oxide (IGZO) channel and a lithium-cobalt oxide (LiCoO x ) ion-supplying layer in the gate oxide. While the device with a thicker (5 nm) tunneling oxide showing a threshold voltage shift (ΔV T) of about 5 V by electron charging upon positive gate voltage (V GS) sweep to +25 V, the device with a 2 nm-thick tunneling oxide exhibits a large memory window with ΔV T > 20 V by Li-ion migration from LiCoO x to IGZO channel, which can be controlled as multilevel states with respect to the V GS amplitude. Incorporation of Li ions into the IGZO channel acting as p-type dopants reduces carrier concentration in the channel and consequently increases V T. The increased V T and the consequently reduced drain current are not instantly restored back by applying negative V GS, featuring WORM memory characteristics. Although the device undergoes partial retention loss, the retention remains up to about 90% after 100 min of retention time. These results verify WORM memory operations in the IGZO TFTs through gate voltage-driven Li-ion incorporation into the IGZO channel to modify its conductive states instead of using a typical electrical charging route.

show abstract

“…In addition, repeated tunneling of the electrons through the tunneling oxide for charging and discharging of the floating gate causes the insulating properties of the tunneling oxide to degrade [4]. Furthermore, the electrostatic crosstalk between adjacent cells in high-density memory architectures generated by the stored charges causes threshold voltage drift [5]. These reliability issues in high-density floating-gate memories and the associated performance limitation come from use of an electrical charge storage-based operating principle to store the data.…”

Section: Introductionmentioning

confidence: 99%

Nonvolatile memory characteristics associated with oxygen ion exchange in thin-film transistors with indium-zinc oxide channel and HfO2-x gate oxide

Han

Jeong

Kim

et al. 2022

Materials Today Advances

View full text Add to dashboard Cite

3X endurance enhancement by advanced signal processor for 3D NAND flash memory

Cited by 5 publications

References 5 publications

Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors

Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors

Write-Once-Read-Many-Times Memory Characteristics with a Large Memory Window Operating at a Low Voltage by Li-Ion Incorporation from the LiCoO_x Ion-Supplying Layer into the InGaZnO Channel of a Thin-Film Transistor

Nonvolatile memory characteristics associated with oxygen ion exchange in thin-film transistors with indium-zinc oxide channel and HfO2-x gate oxide

Contact Info

Product

Resources

About

3X endurance enhancement by advanced signal processor for 3D NAND flash memory

Cited by 5 publications

References 5 publications

Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors

Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors

Write-Once-Read-Many-Times Memory Characteristics with a Large Memory Window Operating at a Low Voltage by Li-Ion Incorporation from the LiCoOx Ion-Supplying Layer into the InGaZnO Channel of a Thin-Film Transistor

Nonvolatile memory characteristics associated with oxygen ion exchange in thin-film transistors with indium-zinc oxide channel and HfO2-x gate oxide

Contact Info

Product

Resources

About

Write-Once-Read-Many-Times Memory Characteristics with a Large Memory Window Operating at a Low Voltage by Li-Ion Incorporation from the LiCoO_x Ion-Supplying Layer into the InGaZnO Channel of a Thin-Film Transistor