3DNAND GIDL-Assisted Body Biasing for Erase Enabling CMOS under Array (CUA) Architecture

Caillat, C.; Beaman, K.L.; Bicksler, A.; Camozzi, Elisa; Ghilardi, Tecla; Huang, Guangyu; Liu, Haitao; Liu, Yifen; Mao, Duo; Mujumdar, Salil; Righetti, Niccolò; Matt, Ulrich; Venkatasubramanian, Chandru; Yang, Xiangyu; Goda, Akira; Gowda, Srivardhan; Mebrahtu, Henok; Sanda, Hiroyuki; Yuwen, Yu; Koval, R. J.

doi:10.1109/imw.2017.7939067

Cited by 31 publications

(12 citation statements)

References 4 publications

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“…In other words, the applied V G is partially consumed by the SOI body and less is available as the voltage across the HZO. One way to remedy this situation is to exploit the GIDL current to inject holes in the floating body [24]. Indeed, as shown in Fig.…”

Section: )) Figs 2(b) and (C)mentioning

confidence: 99%

Highly Scaled, High Endurance, Ω-Gate, Nanowire Ferroelectric FET Memory Transistors

Bae

Kwon

Jeon

et al. 2020

IEEE Electron Device Lett.

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In this work, we demonstrate highly scaled, non-volatile memory transistors with ferroelectric Zr-doped HfO 2 (HZO) as gate insulator.-gate transistors with gate length ∼30 nm and width ∼85 nm were fabricated on ∼20 nm thick SOI. We demonstrate robust memory operation with ≤100 ns program and erase speed at ±5 V, projected memory retention time up to 10 years at 85 • C, and ∼0.5 V memory window after 10 8 endurance cycles. The impact of V D on erase speed provides insights into the importance of holes on memory operation.

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Section: )) Figs 2(b) and (C)mentioning

confidence: 99%

Highly Scaled, High Endurance, Ω-Gate, Nanowire Ferroelectric FET Memory Transistors

Bae

Kwon

Jeon

et al. 2020

IEEE Electron Device Lett.

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Section: Simulation Frameworkmentioning

confidence: 99%

“…The bulk FeFET requires higher doping in order to constrain the short channel effects, and maintain low OFF state leakage which is essential for ensuring proper array operation[15]. While conventional SOI transistors (which have a floating body) usually use lower channel doping, a higher substrate doping is required in case of the SOI FeFET to ensure sufficient GIDL current during the program operation (i.e., to write the high V T state) in order to supply hole carriers to the channel[24],[25].In contrast to the stand-alone MFM capacitors, the additional capacitive contributions in the FeFET arising from the interlayer capacitance (C IL ) and semiconductor capacitance (Cs) take up a significant portion of the applied gate voltage (V GS ) which consequently reduces the net voltage drop across the ferroelectric layer (V FE ). The reduced V FE along with the condition for charge conservation in the gate stack results in the ferroelectric operating on a minor loop trajectory with reduced charge and hysteresis in comparison to the saturation loop.…”

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confidence: 99%

Evaluation of Bulk and SOI FeFET Architecture for Non-Volatile Memory Applications

Mallick

Shukla

2019

IEEE J. Electron Devices Soc.

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The stress induced by the capping electrode is critical to stabilizing the ferroelectric phase in Si-doped HfO 2 which is being actively explored for embedded non-volatile memory applications. While TiN is commonly used as the electrode of choice owing to its thermodynamic stability with HfO 2 , its work function (WF) (=4.8eV) results in reduced memory window (MW), and higher interlayer field (E IL ) in bulk Ferroelectric FETs (FeFETs). This is attributed to the built-in electric-field that arises from the WF difference between the metal and the semiconductor. This effectively reduces the ferroelectric hysteresis, and thus, the MW at the read current. Optimizing the MW and the E IL would entail changing the WF, and thus, the capping electrode-essential to retaining the desired ferroelectric properties. We, therefore, propose using the silicon on insulator (SOI)-FeFET architecture which provides an additional knob-back-gate bias (V bg )-to optimize the MW while reducing the E IL . Further, we show that unlike the bulk FeFET, where a small deviation from the optimal WF dramatically shrinks the MW, the SOI-FeFET facilitates a relatively constant MW over a wide range of V bg . Thus, the SOI-FeFET simplifies the MW & E IL optimization and provides an improved MW versus E IL trade-off in comparison to the bulk FeFET. INDEX TERMS Ferroelectric FET (FeFET), interlayer field (E IL ), memory window (MW), silicon on insulator (SOI), non-volatile memory (NVM).

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“…Since then, the GIDL erase has faced challenges related to the variability and uniformity of the erase potential due to the indirect bias of GIDL erase caused by the potential drop for band-to-band tunneling. Caillat et al proposed an optimization method for GIDL erase with dual-side (bottom select gate side and top select gate side) GIDL injection, which led to better erase effectiveness and more effective tail control of the erase threshold voltage distribution for variability improvement [ 13 ]. Malavena et al studied the GIDL erase dynamics process in the vertical channel NAND Flash, focusing on the increase in channel potential, and proposed a compact model for the dynamic process of the GIDL erase to explore the directions for continuous optimization [ 14 , 15 ].…”

Section: Introductionmentioning

confidence: 99%

Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash

et al. 2023

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The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash. The relationship between the drain-to-body potential (Vdb) of GIDL transistors and the increasing number of layers was studied to explain the reason for the self-adaption of the GIDL erase. The dynamics controlled by the drain-to-body and drain-to-gate potential contribute to the self-adaption of the GIDL erase. Increasing the number of layers leads to a longer duration of the maximum value of Vdb (Vdb_max), combined with the increased drain-to-gate potential, which enhances the GIDL current and further boosts channel potential to reach the same value at different positions of the NAND string. We proposed a method based on the correlation between the duration of Vdb_max and the number of layers to obtain the limited layers of the GIDL erase. The limited layers allowed are more than four times the number of layers used in the current simulation. Combining the novel method of dividing the channel into multi-regions with the asynchronous GIDL erase method will be useful for further stacking more layers in 3D NAND Flash.

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3DNAND GIDL-Assisted Body Biasing for Erase Enabling CMOS under Array (CUA) Architecture

Cited by 31 publications

References 4 publications

Highly Scaled, High Endurance, Ω-Gate, Nanowire Ferroelectric FET Memory Transistors

Highly Scaled, High Endurance, Ω-Gate, Nanowire Ferroelectric FET Memory Transistors

Evaluation of Bulk and SOI FeFET Architecture for Non-Volatile Memory Applications

Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash

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