3D system-on-a-chip design with through-silicon-via-less power supply using highly doped silicon via

Abstract

A low-cost power supply technique for a 3D system-on-a-chip (SoC) is experimentally confirmed by using highly doped silicon via (HDSV). A 100 × 100 μm2 HDSV in a 2 μm thick silicon wafer exhibits a resistance of 2.7 Ω after wafer thinning, bonding, and annealing. A 9-stack 3D SoC is designed with an HDSV power supply, and its area overhead is calculated as 11%. Moreover, technology computer-aided design simulations show that the resistance of the same HDSV could be as low as 22 mΩ, which turns into an area overhead of 0.09%. This work shows detailed experimental results of wafer bonding and current–voltage (IV) characteristics and discusses the applied 3D SoC design.

Proximity Wireless Communication Technologies: An Overview and Design Guidelines

“…The power supply has mostly relied on traditional means such as wire bond and TSV, which might degrade the cost advantage of the inductive coupling communication. To eliminate the use of TSV in the power supply, active research is underway on high-density technologies such as highly doped silicon via (HDSV), which uses a highly doped silicon area as a conducting via to supply power [59], or an ultra-thin fanout wafer level package [60]. For example, the HDSV power supply in 8-SRAM chip stacking is described [59].…”

“…To eliminate the use of TSV in the power supply, active research is underway on high-density technologies such as highly doped silicon via (HDSV), which uses a highly doped silicon area as a conducting via to supply power [59], or an ultra-thin fanout wafer level package [60]. For example, the HDSV power supply in 8-SRAM chip stacking is described [59]. A single SRAM chip consumes 50 mA per chip including TCI channels.…”