Proximity Wireless Communication Technologies: An Overview and Design Guidelines

Kosuge, Atsutake; Kuroda, Tadahiro

doi:10.1109/tcsi.2022.3210200

Cited by 5 publications

(1 citation statement)

References 61 publications

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“…The building block type computation system utilizing the chip-to-chip wireless communication technology [1][2][3][4][5] called Through Chip Interface (TCI) [6][7][8][9] offers the advantage of easy addition, replacement, and removal of stacked chips.TCI utilizes electromagnetic induction occurring between stacked coils (inductors) to enable chip-to-chip wireless communication. As a result, it offers greater flexibility in implementation compared to wired communication methods such as Through Silicon Vias (TSV) or wire bonding.…”

Section: Introductionmentioning

confidence: 99%

TCI Tester: A Chip Tester for Inductive Coupling Wireless Through-Chip Interface

Kayashima

Amano

2023

JLPEA

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The building block computation system is constructed by stacking various chips three-dimensionally. The stacked chips incorporate the same TCI IP (Through Chip Interface Intellectual Property) but cannot provide identical characteristics, requiring adjustments in power supply and bias voltage. However, providing characteristics measurement hardware for all chips is difficult due to the limitation of chip area or pin numbers. To address this problem, we developed TCI Tester, a small chip to measure electric characteristics by stacking on TCI of every chip. By stacking two TCI Tester chips, it appears that the up-directional data transfer has a stricter condition than down directional one on power supply voltage and operational frequency. Also, the transfer performance is poorer than designed. Similar measurement results are obtained by stacking TCI Tester on other chips with TCI IP. To investigate the reason, we analyzed the power grid resistance of various chips with the TCI IP. Results also showed that the chips with higher resistance have a narrow operational condition and poorer performance. The results suggest that the power grid design is important for keeping the performance through the TCI channel.

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Section: Introductionmentioning

confidence: 99%

TCI Tester: A Chip Tester for Inductive Coupling Wireless Through-Chip Interface

Kayashima

Amano

2023

JLPEA

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Silicon Process Technology Constraints for Standardized Vertical Die-to-Die Interconnects

Liew

Sheikh

Kehlet

et al. 2023

2023 IEEE Custom Integrated Circuits Conference (CICC)

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Analysis of Discrete-Time Integrating Amplifiers as an Alternative to Continuous-Time Amplifiers in Broadband Receivers

Ray,

Sen

2023

IEEE Open J. Circuits Syst.

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Recent advancements in low power and low noise front-end amplifiers have made it possible to support high-speed data transmission within the deep roll-off regions of conventional wireline channels. Despite being primarily limited by inter-symbol-interference (ISI), these legacy channels also require power-consuming front-end amplifiers due to increased insertion-loss at high frequencies. Wireline-like broadband channels, such as proximity communication and human-body-communication (HBC), as well as multi-lane, densely-packed channels, are further constrained by their high loss and unique channel responses which cause the received signal to be noise-limited. To address these challenges, this paper proposes the use of a discrete-time integrating amplifier as a low power (<1pJ/b using 65nm CMOS up to 5-6 Gb/s) alternative to traditional continuous-time front-end amplifiers. Integrating amplifiers also reduce the effects of noise due to its inherent current integrating process. The paper provides a detailed mathematical analysis of gain of two conventional and three novel and improved integrating amplifiers, accurate input referred noise estimations, signal-to-noise ratio, and a comparison of the integrating amplifier's performance with that of a low-noise amplifier. The analysis identifies the most optimum integrator architecture and provides comparison with simulated results. This paper also develops theoretical expressions and provides in-depth understanding of input referred noise, while supporting them by simulations using 65nm CMOS technology node. Finally, a comparative analysis between low-noise amplifier and discrete-time integrating amplifier is presented to demonstrate power and noise benefits for both legacy and wireline-like channels, while providing an easier design space as integrator provides two-dimensional controllability for gain.

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Proximity Wireless Communication Technologies: An Overview and Design Guidelines

Cited by 5 publications

References 61 publications

TCI Tester: A Chip Tester for Inductive Coupling Wireless Through-Chip Interface

TCI Tester: A Chip Tester for Inductive Coupling Wireless Through-Chip Interface

Silicon Process Technology Constraints for Standardized Vertical Die-to-Die Interconnects

Analysis of Discrete-Time Integrating Amplifiers as an Alternative to Continuous-Time Amplifiers in Broadband Receivers

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