A 7-nm FinFET 1.2-TB/s/mm<sup>2</sup> 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver

Shiba, K.; Okada, Michiyo; Kosuge, Atsutake; Hamada, Mototsugu; Kuroda, Tadahiro

doi:10.1109/jssc.2022.3224421

Cited by 6 publications

(8 citation statements)

References 33 publications

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“…Several near-memory architectures have been proposed to address the memory wall problem by reducing the distance between computation and memory [11][12][13]. In particular, in the near-memory architectures where standard highdensity memory and logic process components are integrated into a single package [14][15][16][17][18], cross-process design and analysis methods become a popular research topic [19][20][21].…”

Section: Introductionmentioning

confidence: 99%

“…Ref. [16] reports a wireless stacked Static Random Access Memory (SRAM) which utilizes semiconductor process coils to establish a vertical data path between four SRAM dies and a logic die, creating a 3D near-memory architecture. In ref.…”

Section: Introductionmentioning

confidence: 99%

“…In ref. [16], there is no metal-based signal interconnect between SRAM dies and the logic die ("Power supplies are provided via bonded wires"). The interconnection between the two different semiconductor processes is achieved through a magnetic field model within the package of this structure.…”

Section: Introductionmentioning

confidence: 99%

“…However, HBM has the lowest vertical stacking density. Wireless stacked SRAM achieves an overlapping layout between the coils of the vertical channel and the memory media, achieving an area efficiency of 1162 GB/s/mm 2 [16], surpassing HBM. The SI analysis of the wireless stacked SRAM structure is conducted on a unit of stacked chips, with interconnections between stacks facilitated by virtual models.…”

mentioning

confidence: 99%

“…Standard Electronics Design Automation (EDA) tools do not support comprehensive SI analysis for these cross-process architectures. To establish sub-micron vertical interconnections between devices of different manufacturing processes, this crossprocess vertical interconnection employs buffer drivers for the vertical interconnect units, rather than I/O circuits of HBMs [14,15] or a virtual model of wireless stacked SRAM [16]. Because of the absence of I/O circuits or a virtual model for segmenting the cross-process structure, the SI analysis of SeDRAM is geared towards buffers, essentially following the design requirements of a standard 2D chip.…”

mentioning

confidence: 99%

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A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM

Jiang,

Jia,

Wang

et al. 2024

Micromachines

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A multi-layer stacked Dynamic Random Access Memory (DRAM) platform is introduced to address the memory wall issue. This platform features high-density vertical interconnects established between DRAM units for high-capacity memory and logic units for computation, utilizing Wafer-on-Wafer (WoW) hybrid bonding and mini Through-Silicon Via (TSV) technologies. This 3DIC architecture includes commercial DRAM, logic, and 3DIC manufacturing processes. Their design documents typically come from different foundries, presenting challenges for signal integrity design and analysis. This paper establishes a lumped circuit based on 3DIC physical structure and calculates all values of the lumped elements in the circuit model with the transmission line model. A Cross-Process Signal Integrity Analysis (CPSIA) method is introduced, which integrates three different manufacturing processes by modeling vertical stacking cells and connecting DRAM and logic netlists in one simulation environment. In combination with the dedicated buffer driving method, the CPSIA method is used to analyze 3DIC impacts. Simulation results show that the timing uncertainty introduced by 3DIC crosstalk ranges from 31 ps to 62 ps. This analysis result explains the stable slight variation in the maximum frequency observed in vertically stacked memory arrays from different DRAM layers in the physical testing results, demonstrating the effectiveness of this CPSIA method.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM

Jiang,

Jia,

Wang

et al. 2024

Micromachines

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A novel high-performance TG-based SRAM cell with 5 nm FinFET technology

Pal,

Upadhyaya,

Majumder

et al. 2024

Eng. Res. Express

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In this study, we investigate the performance and reliability of a novel static random-access memory (SRAM) cell utilizing advanced 5 nm FinFET technology. Our research aims to address critical challenges in SRAM design by integrating transmission gates and power gated transistors. Through extensive simulations using the Cadence Virtuoso tool, we optimize the SRAM cell’s read and write paths, resulting in substantial improvements in both functionalities. Additionally, our study unveils temperature-dependent variations in the read current and write margin, emphasizing the influence of temperature on SRAM performance. Compared to conventional FinFET SRAM circuits of equivalent bit-cell area and read latency, our innovative design showcases remarkable improvements across various parameters. Specifically, we achieve a commendable increase of 6.16% in the write static noise margin (WSNM) and 5.86% in the hold static noise margin (HSNM). Moreover, our findings reveal a substantial boost in read stability, increasing from 14.75% to 18.35%. These advancements underscore the promising potential of our approach in paving the way for future innovations in high-performance memory architectures. By leveraging state-of-the-art technology and meticulous optimization techniques, our research sets a new standard for SRAM design, offering enhanced performance, reliability, and efficiency in memory systems.

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An In-Situ Dynamic Quantization With 3D Stacking Synaptic Memory for Power-Aware Neuromorphic Architecture

et al. 2023

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A 7-nm FinFET 1.2-TB/s/mm² 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver

Cited by 6 publications

References 33 publications

A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM

A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM

A novel high-performance TG-based SRAM cell with 5 nm FinFET technology

An In-Situ Dynamic Quantization With 3D Stacking Synaptic Memory for Power-Aware Neuromorphic Architecture

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A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver

Cited by 6 publications

References 33 publications

A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM

A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM

A novel high-performance TG-based SRAM cell with 5 nm FinFET technology

An In-Situ Dynamic Quantization With 3D Stacking Synaptic Memory for Power-Aware Neuromorphic Architecture

Contact Info

Product

Resources

About

A 7-nm FinFET 1.2-TB/s/mm² 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver