3D Simulation study of gate coupling and gate cross-interference in advanced floating gate non-volatile memories

Ghetti, A.; Bortesi, L.; Vendrame, L.

doi:10.1016/j.sse.2005.10.014

Cited by 27 publications

(10 citation statements)

References 1 publication

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“…Fig. 3 reports the experimental trends of the two members of the aforementioned equation as a function of the device current (cell capacitance has been estimated ∼5.3 · 10 −17 F by means of technology computer-aided design 3-D simulation tools [9]). We observed a similar dependence with a lift, in terms of intensity, of up to more than one order of magnitude (giant RTS).…”

Section: Experimental Data and Discussionmentioning

confidence: 99%

Giant Random Telegraph Signals in Nanoscale Floating-Gate Devices

Fantini

Ghetti

Marinoni

et al. 2007

IEEE Electron Device Lett.

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The magnitude of a random telegraph signal (RTS) in nanoscale floating-gate devices has been experimentally investigated as a function of carrier concentration. Discrete current switching, which is caused by a single trap, has been found to be almost one order of magnitude higher with respect to what was predicted by the classical theory of carrier number and correlated mobility fluctuations. Nevertheless, the trap signature well fits the typical SiO 2 trap spectroscopy. In addition, the rigid shift between the transfer curves related to filled-and empty-trap state, together with the normalized current fluctuation dependence on the channel carrier density, suggests that a pure number fluctuation is the correct theoretical interpretative framework. Thus, we propose a possible physical explanation for such a giant RTS on the basis of a quasi-1-D current filamentation.Index Terms-Flash memory, nanoscale device, noise, random telegraph signal (RTS).

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Section: Experimental Data and Discussionmentioning

confidence: 99%

Giant Random Telegraph Signals in Nanoscale Floating-Gate Devices

Fantini

Ghetti

Marinoni

et al. 2007

IEEE Electron Device Lett.

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“…This parasitic interference increasingly jeopardizes the planar NAND Flash memories parametric and functional yield. Parasitic capacitive couplings can be estimated only by TCAD simulations, because it is not practical to directly extract them from FG NAND memory devices [5][6][7]. The direct measurements of cross-cell interference require expensive, custom made test ICs and methodologies [8].…”

Section: Introductionmentioning

confidence: 99%

Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness

Poliakov

Blomme

Corbalan

et al. 2011

Microelectronics Reliability

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“…2, the J e and electrostatic potential at the channel edge region are slightly increased due to the tip effect and the effect of the electric field from the recessed control gate when adjacent BL cells are in a fresh state. However, we can notice that the electric field from the floating gate of adjacent BL cells is more dominant by comparing the electrostatic potential and J e in the fresh state with those in E/P mode when a V th of the read cell is nearly 0 V [13]. are 1 Å, 16 nm, and 4 nm, respectively.…”

Section: Resultsmentioning

confidence: 99%

The Effect of Adjacent Bit-Line Cell Interference on Random Telegraph Noise in nand Flash Memory Cell Strings

Joe

Jeong

et al. 2012

IEEE Trans. Electron Devices

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The effect of adjacent bit-line (BL) cell interference on BL current fluctuation (ΔI BL = high I BL − low I BL ) due to random telegraph noise (RTN) in floating-gate NAND Flash cell strings is characterized. It was found that the electron current density (J e ) of a read cell can be appreciably different depending on the position in the channel width direction because of the interference from adjacent BL cells. The interference can be controlled by the state (program or erase) of the adjacent cells. We verified that ΔI BL due to RTN increases as a high-J e position is controlled to be close to a trap position in 32-nm NAND Flash memory strings. Finally, it was also shown that the adjacent cell interference affects not only ΔI BL but also the ratio of capture and emission time constants [ln(τ c /τ e )].Index Terms-Bit-line (BL) current fluctuation, BL interference, capture and emission, floating gate, NAND Flash memory, random telegraph noise (RTN).

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3D Simulation study of gate coupling and gate cross-interference in advanced floating gate non-volatile memories

Cited by 27 publications

References 1 publication

Giant Random Telegraph Signals in Nanoscale Floating-Gate Devices

Giant Random Telegraph Signals in Nanoscale Floating-Gate Devices

Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness

The Effect of Adjacent Bit-Line Cell Interference on Random Telegraph Noise in nand Flash Memory Cell Strings

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