3D Simulation Study of Cell-Cell Interference in Advanced NAND Flash Memory

Liu, Haitao; Groothuis, S.; Mouli, Chandra; Li, Jian; Parat, Krishna; Krishnamohan, Tejas

doi:10.1109/wmed.2009.4816143

Cited by 17 publications

(7 citation statements)

References 4 publications

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“…As the technology continues to scale down and, hence, adjacent cells become closer, the parasitic coupling capacitance between adjacent cells continues to increase and results in increasingly severe cell-to-cell interference. Recent studies [8]- [10] have clearly identified cell-to-cell interference as the major challenge for future NAND Flash memory scaling.…”

Section: B Cell-to-cell Interferencementioning

confidence: 99%

“…By letting denote the expected threshold voltage of the th interfering cell after programming and denote the mean of the erased state, we can predict the cell-to-cell interference experienced by the victim cell as (10) By letting denote the target verify voltage of the victim cell in programming operation, we can predistort the victim cell by shifting the verify voltage from to . Through such data predistortion processing, we can expect that the threshold voltage of the victim cell will be shifted toward its desired location after the occurrence of cell-to-cell interference.…”

Section: Technique Ii: Data Predistortionmentioning

confidence: 99%

“…It has been well recognized that cell-to-cell interference has become the major source for floating-gate threshold-voltage distribution distortion [8]- [10]. As elaborated in Section II-B, cell-to-cell interference is a deterministic data-dependent process, which can be mathematically described with a simple formula.…”

Section: Introductionmentioning

confidence: 99%

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Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory

Dong

Shu

Zhang

2010

IEEE Trans. Circuits Syst. I

130

112

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With the appealing storage-density advantage, multilevel-per-cell (MLC) NAND Flash memory that stores more than 1 bit in each memory cell now largely dominates the global Flash memory market. However, due to the inherent smaller noise margin, the MLC NAND Flash memory is more subject to various device/circuit variability and noise, particularly as the industry is pushing the limit of technology scaling and a more aggressive use of MLC storage. Cell-to-cell interference has been well recognized as a major noise source responsible for raw-memory-storage reliability degradation. Leveraging the fact that cell-to-cell interference is a deterministic data-dependent process and can be mathematically described with a simple formula, we present two simple yet effective data-processing techniques that can well tolerate significant cell-to-cell interference at the system level. These two techniques essentially originate from two signal-processing techniques being widely used in digital communication systems to compensate communication-channel intersymbol interference. The effectiveness of these two techniques have been well demonstrated through computer simulations and analysis under an information theoretical framework, and the involved design tradeoffs are discussed in detail.

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Section: B Cell-to-cell Interferencementioning

confidence: 99%

Section: Technique Ii: Data Predistortionmentioning

confidence: 99%

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Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory

Dong

Shu

Zhang

2010

IEEE Trans. Circuits Syst. I

130

112

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“…This is referred to as cell-to-cell interference, which has been well recognized as the one of major noise sources in NAND flash memory [17][18][19]. Threshold voltage shift of a victim cell caused by cell-to-cell interference can be estimated as [16] …”

Section: Cell-to-cell Interferencementioning

confidence: 99%

Reducing latency overhead caused by using LDPC codes in NAND flash memory

Zhao

Dong²,

Sun

et al. 2012

EURASIP J. Adv. Signal Process.

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Semiconductor technology scaling makes NAND flash memory subject to continuous raw storage reliability degradation, leading to the demand for more and more powerful error correction codes. This inevitable trend makes conventional BCH code increasingly inadequate, and iterative coding solutions such as low-density parity-check (LDPC) codes become very natural alternative options. However, fine-grained soft-decision memory sensing must be used in order to fully leverage the strong error correction capability of LDPC codes, which results in significant data access latency overhead. This article presents a simple design technique that can reduce such latency overhead. The key is to cohesively exploit the NAND flash memory wear-out dynamics and impact of LDPC code structure on decoding performance. Based upon detailed memory device modeling and ASIC design, we carried out simulations to demonstrate the potential effectiveness of this design method and evaluate the involved trade-offs.

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“…All this has, however, remained speculative as the degradation of I -V characteristics is a complicated process involving Q FG shift, the generation of Q OX , and the interface states. Since NAND Flash memory cells are getting less reliable because of reduction of cell capacitance due to the gate area scaling and enlargement of neutral V t distribution by short and narrow channel effects, it is now crucial to obtain more qualitative insights into the origin of the degradation in reliability [11]- [13]. In this paper, to make the quantitative study about the degradation of gate oxide by the P/E cycles, a new method to extract net Q FG and vertical profile of Q OX is proposed.…”

Section: Introductionmentioning

confidence: 99%

New Method to Analyze the Shift of Floating Gate Charge and Generated Tunnel Oxide Trapped Charge Profile in NAND Flash Memory by Program/Erase Endurance

Shirota

Yang

Chen

et al. 2015

IEEE Trans. Electron Devices

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A new test system was devised and used to separate the amount of floating gate (FG) charge ( Q FG ) from the oxide trapped charge ( Q OX ) generated by program-anderase (P/E) cycles. We also extracted the pure V mid shift caused by the generation of Q OX , which is separated from the part of V t shift coming from Q FG deviation. The identification of Q FG and V mid shift makes it possible to analyze the detailed the oxide trapped charge profile. The Q FG shift generated by P/E cycles displays asymmetry between the programmed and erased states: the absolute value of Q FG exhibits a maximum at ∼100 cycles in the programmed states, while Q FG monotonically decreases in the erased one. Considering that the Fowler-Nordheim tunneling current is sensitive to the oxide trap near the cathode, itself the source of electron tunneling current, our results indicate that the hole trap is dominant near to Si, whereas the electron trap is dominant near FG.

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3D Simulation Study of Cell-Cell Interference in Advanced NAND Flash Memory

Cited by 17 publications

References 4 publications

Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory

Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory

Reducing latency overhead caused by using LDPC codes in NAND flash memory

New Method to Analyze the Shift of Floating Gate Charge and Generated Tunnel Oxide Trapped Charge Profile in NAND Flash Memory by Program/Erase Endurance

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