3D modelling based comprehensive analysis of high- κ gate stack graded channel dual material trigate MOSFET

Int J Numerical Modelling

2019

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The semiconductor industry has implemented the technique of wrapping the gate electrode on different sides of channel to mitigate the degrading electrostatic effects in nanometer transistor. Intel adopted trigate architecture, wherein the channel is surrounded by gate electrode on three sides to improve the gate control over the channel. In order to further enhance the performance and diminish the short channel effects, triple material trigate silicon-oninsulator (SOI) MOSFET is explored in this work. An analytical model to determine the device electrostatics and match deviations due to device geometry has also been developed. The consequence of quantum confinement effects (QMEs), which arise due to ultra-thin body structure, on the inversion charge and threshold voltage has also been included. Thus, the analytical model presented in this work is based on a self-consistent solution of threedimensional Poisson's equation and two-dimensional Schrodinger equation with proper boundary conditions. The model is verified by the uniformity obtained between the results from analytical model and TCAD simulations. The superiority of the device has been demonstrated by comparing performance parameters like potential distribution, field variations, drain induced barrier lowering (DIBL) with already existing device structures like single material trigate (SMTG) and dual material trigate (DMTG) SOI MOSFETs

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Section: Resultsmentioning

confidence: 99%

Three‐dimensional analytical modeling and performance analysis of triple material trigate silicon‐on‐insulator MOSFET

Int J Numerical Modelling

2019

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“…The threshold voltage V th Cl without considering quantum effects can be modelled from the surface potential profile for that value of VGS at which the minimum surface potential equals twice fermipotential [19,20]…”

Section: Analytical Modellingmentioning

confidence: 99%

“…The electric field profile is modelled as in [18]

scriptF = - \frac{normald ϕ_{s} ()(, x)}{normald x} = η ψ_{2} {normale}^{- η x} - η ψ_{1} {normale}^{- η x}

The threshold voltage

()(, V_{th}^{Cl})

without considering quantum effects can be modelled from the surface potential profile for that value of VGS at which the minimum surface potential equals twice fermi‐potential [19,20]

{ϕ_{s} (x_{min})|}_{V_{GS} = V_{th}} = 2 ϕ_{F}

where

ϕ_{F}

is the Fermi potential.…”

Section: Analytical Modellingmentioning

confidence: 99%

Analytical modelling and performance analysis of gate‐ and channel‐engineered trapezoidal trigate MOSFET

IET Circuits, Devices & Systems

2019

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Here, the authors propose an analytical model to evaluate the performance of an advanced trigate MOSFET structure called trapezoidal trigate MOSFET on silicon-on-nothing (TTMSON). The model is based on the solution of Poisson's partial differential equation in three dimensions. The expression for potential distribution has been used to model other device parameters like electric field distribution, quantum inversion charge, and threshold voltage. The TTMSON device immunity to various short channel effects (SCEs), such as drain-induced barrier lowering (DIBL) and sub-threshold swing, has been examined. A detailed analysis of the gate and channel engineering techniques like dual material gate, graded channel, and dual material gate with graded channel has also been carried out to choose the best device structural configuration for enhancing the device performance and mitigating SCEs in nano-regime. In addition, the effect of inclination angle on different performance parameters has been considered. The proposed analytical model of TTMSON has been verified by comparing the model results with the simulation results using the numerical device simulator ATLAS.

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Quasi-analytical model-based performance analysis of dual material gate stack strained GAA FinFET

International Journal of Electronics Letters

2019