3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory

Abstract

Abstract-Shared L1 memories are of interest for tightlycoupled processor clusters in programmable accelerators as they provide a convenient shared memory abstraction while avoiding cache coherence overheads. The performance of a shared-L1 memory critically depends on the architecture of the low-latency interconnect between processors and memory banks, which needs to provide ultra-fast access to the largest possible L1 working set. The advent of 3D technology provides new opportunities to improve the interconnect delay and the form factor. In this paper we propose a network architecture, 3D-LIN, based on 3D integration technology. The network can be configured based on user specifications and technology constraints to provide fast access to L1 memories on multiple stacked dies. The extracted results from the physical synthesis of 3D-LIN permit to explore trade-offs between memory size and network latency from a planar design to multiple memory layers stacked on top of logic. In the case where the system memory requirements lead to a memory area that occupies 60% of the chip, the form factor can be reduced by more than 60% by stacking 2 memory layers on the logic. Latency reduction is also promising: the network itself, configured for connecting 16 processing elements to 128 memory banks on 2 memory layers is 24% faster than the planar system.

A case for three‐dimensional stacking of tightly coupled data memories over multi‐core clusters using low‐latency interconnects

“…Performance limitations of the interconnection networks have led to a renewed interest in interconnect research and a transition from traditional bus-based systems to more sophisticated topologies, including mesh NoCs [8], hierarchical bus models [9], flattened butterfly on-chip networks [10] and crossbars [11][12][13]. The ability of crossbars to provide uniform access latency makes them an appealing option in processor-to-L1 memory interface for limited-cardinality clusters (16 PEs, typically), because predictable access latencies allow for quality-of-service guarantees and ease of programming.…”

“…The key difference between our proposed approach and these works is modularity, which allows stacking of several memory dies on a logic die without the need for new masks for each stacked die. Moreover, our solutions offer better scalability compared with [13] (more in-depth discussion is performed in Sections 4 and 6.2). Additionally, physical synthesis on realistic 3D floorplans make our obtained results more accurate.…”

“…It should be noted that in the 3D network presented in [13], interconnects are replicated completely in each memory layer, and a copy of the arbitration circuits for each layer is placed on the logic layer. As a result, addition of new memory layers, increases 'BankingFactor', and therefore the size of the logic-die grows.…”

“…In order to explain this, consider the 2D planar design with 2 MB of memory, for which we obtained a maximum between micro-bumps and direct copper bonding without protection circuits, it can be estimated that micro-bumps and protection circuits further drop the performance by a factor of about 9%, consuming 0.21 ns of the critical path. One last point to mention is that, system latency in [13] is calculated as (network latency + memory access time), and by maintaining a fixed 'BankingFactor' (reduction in number of banks per layers by addition of new layers), it has been shown that both system and network latency decrease significantly. Whereas in our experiments, we showed that a major contributor to the performance drop is the latency of the TSVs and their drivers; and in order to support our argument, we performed timing characterisation of the whole 3D stack considering the TSV loads and their driver circuits, and derived maximum achievable frequency directly from the post-layout results of the physical synthesis tool.…”

“…In addition, 3D extension of low‐latency crossbars for shared L1 clusters has been investigated in [11, 13], whereas [16] uses time‐division multiplexing buses for this purpose. The key difference between our proposed approach and these works is modularity, which allows stacking of several memory dies on a logic die without the need for new masks for each stacked die.…”