A case for three‐dimensional stacking of tightly coupled data memories over multi‐core clusters using low‐latency interconnects

Abstract

Shared tightly coupled data memories are key architectural elements for building multi-core clusters in programmable accelerators and embedded systems, as they provide a convenient shared memory abstraction while avoiding cache coherence overheads. The performance of these memories largely depends on the architecture of the interconnect used between processing elements (PEs) and memory banks. The advent of three-dimensional (3D) technology has provided new opportunities to increase design modularity and reduce latency and manufacturing cost. In this study, the authors propose two 3D network architectures: C-logarithmic interconnect (LIN) and Distributed logarithmic interconnect (D-LIN) (designed in synthesisable RTL), which allow modular stacking of multiple L1 memory dies over a multi-core cluster with a limited number of PEs. The authors have used two through-silicon-via technologies: the state-of-the-art micro-bumps and the promising and dense Cu-Cu direct bonding. The overhead of electrostatic discharge protection circuits has been considered, as well. Architectural simulation results demonstrate that, in processor-to-L1-memory context, C-LIN and D-LIN perform significantly better than traditional network-on-chips and simple time-division multiplexing buses. Furthermore, post-layout results show that the proposed 3D architectures achieve comparable speed against their 2D counterparts, whereas enabling modularity: from 256 kB to 2 MB L1 memory configurations with a single mask set.

A Modular Shared L2 Memory Design for 3-D Integration

“…RE is responsible for decoding request packets and issuing them to the memory pipeline (only aligned access is supported). ATs are combinational binary trees adopted from the logarithmic interconnect [13], and finally, response engines receive response packets from RB and serialize them through multiple flits to the NIs. All components, which perform arbitration, have been designed carefully to avoid starvation.…”

“…L1 SPMs offer very low latency access (1-2 Cycles) to a cluster of tightly coupled processors. However, their 3-D stacking is not so beneficial with current TSV technologies, because their access latency directly affects processor pipeline, and moving toward, the third dimension requires propagation of combinational signals through stacked TSVs [13], which are not yet much better in terms of speed than global on-chip wires [14]. Therefore, lower sensitivity of L2 SPMs to access latency and its variations makes them a more interesting option for going toward the third dimension.…”

“…The 3-D stacked SPMs have been studied in [13], [31], [32], and [33]. Saito et al [31] proposed a configurable MD that consists of many uniform memory elements, which are connected to each other with a switch-based 3-D mesh interconnection network.…”

“…Each processor core is directly connected to each 4 kB of SRAM scratchpad data memory. While these papers focus on 3-D stacking of private memory banks, [13] uses low latency logarithmic interconnect to connect a LD, composed by processing elements (PEs), to a stack of shared L1 SPM memories in a modular fashion from 256 kB to 2 MB. In addition, in [33], a similar logarithmic interconnect provides low latency access to a stack of L2 SPM dies.…”

Design of Efficient Pipelined Router Architecture for 3D Network on Chip

“…The latter are getting more complex demanding a higher performance system to handle parallel computing and provide higher bandwidth. At the same time, semiconductor industries are exploiting three dimensional integrated circuits (3D IC) which provide short global interconnects, lower power consumption, and higher performance [5]. Bringing together 2D NoC architecture with 3D IC technology, makes the design of 3D NoC possible which is a stack multiple die in the vertical axis that are interconnected through silicon via (TSV) [6].…”