3D Integration Techniques Applied to SiGe Power Amplifiers

Abstract

We describe a 0.35 µm SiGe BiCMOS technology that is optimized for power amplifier (PA) applications. The key feature of this technology is a novel low inductance ground to the package by method of through-silicon-via (TSV), offering a competitive solution for future multi-band / multi-mode PA integration. The tungsten filled, multi-finger, bar shaped TSV delivers over 75% reduction in inductance compared to a traditional wire bond, enabling higher frequency applications with roughly 20% die area reduction, and without compromising the technology reliability for use conditions in a low-cost plastic QFN package. In this paper we demonstrate the commercial feasibility of the TSV, its RF performance, and its usefulness in a demanding WiMAX PA application.

Stress Characterization of Tungsten-Filled Through Silicon via Arrays Using Very High Resolution Multi-Wavelength Raman Spectroscopy

“…[1] This paper focuses on stress in Si adjacent to grounded TSVs, where the TSVs are electrically grounded to the silicon substrate (i.e., no insulator between the TSV and the silicon substrate). The grounded TSVs, processed on the wafer front side, are used in conjunction with blanket wafer backside metallization to reduce ground lead inductance in analog and mixed signal technologies [2]. The TSVs in this study are 150 μm deep, to minimize packaging complexity and eliminate the need for a handle wafer during backside grinding and wafer packaging.…”

“…The TSVs in this study are 150 μm deep, to minimize packaging complexity and eliminate the need for a handle wafer during backside grinding and wafer packaging. Bipolar-complementary-metal-oxidesemiconductor (BiCMOS) SiGe power amplifiers, at 5.8 GHz, using grounded TSVs and low cost wire bond packages were first qualified for manufacturing in 2007 and numerous production designs have been successfully implemented [2]. However, stress associated with the TSV is still a challenge for the integration of grounded TSVs, in terms of minimizing wafer warpage and bow.…”