Modular integration of annular TSV structures filled with tungsten in a 0.25μm SiGe:C BiCMOS technology

Marschmeyer, S.; Berthold, J.; Krüger, Andreas; Lisker, Marco; Scheit, A.; Schulze, Sebastian; Trusch, A.; Wietstruck, Matthias; Wolansky, D.

doi:10.1016/j.mee.2014.09.020

Cited by 10 publications

(7 citation statements)

References 5 publications

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“…The structures were manufactured by Deep Reactive Ion Etching (DRIE) with the Bosch process: isotropic dry etching with sulfur hexafluoride, SF 6 at 2°C cathode temperature, and sidewall passivation by polymer deposition with octafluorocyclobutane and oxygen, C 4 F 8 /O 2 , in the tool Tegal 200 (SPTS) [4]. The deposition and etch time in each cycle were 1.0 and 1.8 s, respectively.…”

Section: Methodsmentioning

confidence: 99%

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Through silicon via profile metrology of Bosch etching process based on spectroscopic reflectometry

Fursenko

Bauer

Marschmeyer

et al. 2015

Microelectronic Engineering

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Section: Methodsmentioning

confidence: 99%

“…Generally, TSVs are formed by etching a vertical via and filling them with a conductive material, such as a copper [1]. TSV technology has opened up new possibilities of 3D integration of micro-electro-mechanical systems (MEMS), photonic circuits, microfluidic devices, or electrical grounding of CMOS and BiCMOS devices [2][3][4].…”

Section: Introductionmentioning

confidence: 99%

Through silicon via profile metrology of Bosch etching process based on spectroscopic reflectometry

Fursenko

Bauer

Marschmeyer

et al. 2015

Microelectronic Engineering

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“…Generally, TSVs are formed by etching a vertical via and filling them with a conductive material, such as copper [1]. TSV technology has opened up new possibilities of 3D integration of micro-electro-mechanical systems (MEMS), photonic circuits, microfluidic devices, or electrical grounding of CMOS and BiCMOS devices [2][3]. The very high aspect ratio (AR) (via depth/via size>10:1) opens up potential of smaller packaging, stress reduction, and low costs for advanced 3D integration.…”

Section: Introductionmentioning

confidence: 99%

Very high aspect ratio through silicon via reflectometry

et al. 2017

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Through Silicon Via (TSV) technology is a key feature of new 3D integration of circuits by creation of interconnections using vias, which go through the silicon wafer. Typically, the highly-selective Bosch Si etch process, characterized by a high etch rate and high aspect ratio and forming of scallops on the sidewalls is used. As presented in this paper, we have developed an experimental setup and a respective evaluation algorithm for the control and monitoring of very high aspect ratio TSV profiles by spectroscopic reflectometry. For this purpose square via arrays with lateral dimension from 3 to 10 µm were fabricated by a Bosch etch process and analyzed by our setup. By exploiting interference and diffraction effects of waves reflected from the top and bottom surfaces as well as from the side walls of the TSV patterns, the measurements provided etch depths, CD values and scallop periods. The results were compared with data obtained by a commercial wafer metrology tool. Aspect ratios of up to 35:1 were safely evaluable by our setup.

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“…However, high stress in deposited tungsten makes it susceptible to delamination which limits the maximum metal thickness to the order of a few microns and restricts the use of tungsten to small-diameter disk-shaped vias or to ring-shaped (annular) vias [25,26,28]. Thus, for fully metal-filled via holes, the use of tungsten is limited to blind vias or vias in very thin substrates.…”

Section: Introductionmentioning

confidence: 99%

Through Silicon Vias With Invar Metal Conductor for High-Temperature Applications

Asiatici

Laakso

Fischer

et al. 2017

J. Microelectromech. Syst.

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Abstract-Through silicon vias (TSVs) are key enablers of 3D integration technologies which, by vertically stacking and interconnecting multiple chips, achieve higher performances, lower power and a smaller footprint. Copper is the most commonly used conductor to fill TSVs; however, copper has a high thermal expansion mismatch in relation to the silicon substrate. This mismatch results in a large accumulation of thermomechanical stress when TSVs are exposed to high temperatures and/or temperature cycles, potentially resulting in device failure.In this paper, we demonstrate 300 µm long, 7:1 aspect ratio TSVs with Invar as a conductive material. The entire TSV structure can withstand at least 100 thermal cycles from -50• C to 190• C and at least one hour at 365 • C, limited by the experimental setup. This is possible thanks to matching coefficients of thermal expansion (CTE) of the Invar via conductor and of silicon substrate. This results in thermomechanical stresses that are one order of magnitude smaller compared to copper TSV structures with identical geometries, according to finite element modelling. Our TSV structures are thus a promising approach enabling 2.5D and 3D integration platforms for high-temperature and harsh-environment applications.

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Modular integration of annular TSV structures filled with tungsten in a 0.25μm SiGe:C BiCMOS technology

Cited by 10 publications

References 5 publications

Through silicon via profile metrology of Bosch etching process based on spectroscopic reflectometry

Through silicon via profile metrology of Bosch etching process based on spectroscopic reflectometry

Very high aspect ratio through silicon via reflectometry

Through Silicon Vias With Invar Metal Conductor for High-Temperature Applications

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