Through Silicon Vias With Invar Metal Conductor for High-Temperature Applications

Abstract

Abstract-Through silicon vias (TSVs) are key enablers of 3D integration technologies which, by vertically stacking and interconnecting multiple chips, achieve higher performances, lower power and a smaller footprint. Copper is the most commonly used conductor to fill TSVs; however, copper has a high thermal expansion mismatch in relation to the silicon substrate. This mismatch results in a large accumulation of thermomechanical stress when TSVs are exposed to high temperatures and/or temperature cycles, potentially resulting in device failure.In this paper, we demonstrate 300 µm long, 7:1 aspect ratio TSVs with Invar as a conductive material. The entire TSV structure can withstand at least 100 thermal cycles from -50• C to 190• C and at least one hour at 365 • C, limited by the experimental setup. This is possible thanks to matching coefficients of thermal expansion (CTE) of the Invar via conductor and of silicon substrate. This results in thermomechanical stresses that are one order of magnitude smaller compared to copper TSV structures with identical geometries, according to finite element modelling. Our TSV structures are thus a promising approach enabling 2.5D and 3D integration platforms for high-temperature and harsh-environment applications.

Invar Electrodeposition for Controlled Expansion Interconnects

“…While there is a lack of literature on the electroplating of INVAR on TSV substrates with controlled composition, a recently published article by Laakso et al describes TSV filling by INVAR using INVAR wire and its assembly to the vias. 10 The method however does not allow for controlling the interface between the rods, which can potentially lead to delaminating of the INVAR and reduction in thermal and electrical resistivity. Despite the progress in filling TSVs with copper and nickel, the methods cannot be approximated for the IN-VAR, due to composition control.…”

“…5,6 Moreover, electroplating has been proven as cost-effective and reliable technique to fabricate micro-and nanostructures on various substrates. [6][7][8][9][10][11][12][13] In this work, we demonstrated electrodeposition of the INVAR alloy with low internal stress and low thermal expansion on different substrates to fabricate redistribution layers (RDL), through silicon vias (TSV) interconnects, pillars, bumps, pads and freestanding foils. We have been using eLOCOS (low cost, scalable and selective) plating process, a nano-and microfabrication electrochemical platform technology developed by NANO3D.…”

Vertical integration of microchips by magnetic assembly and edge wire bonding

“…Other approaches for out-of-plane 3D assembly of structures without direct contact utilize stochastic self-assembly principles to place discrete components on a surface or into a template of holes, based on magnetic attraction [24][25][26] , dynamic force fields provided by gravitational and magnetic forces 27 , and controlled vibration stimuli 28 . In particular, to perform out-of-plane assembly of discrete components into receiving holes, vertical insertion of components into through-silicon trenches using magnetic assembly has been proposed 29 , as well as magnetic assembly of ferromagnetic metallic wires for through-substrate vias [30][31][32] . The use of magnetic assembly is of particular interest for microchip handling, because it allows non-contact manipulation of microchips.…”

Inkjet printing technology for increasing the I/O density of 3D TSV interposers

“…The drawbacks of incorporating such metals are the reliability issues due to the different CTE values of the involved materials, for example, Cu or Au and Si. The difference in the CTE values of Cu (16.7 p.p.m.°C − 1 ) and Si (2.5 p.p.m.°C − 1 ) 5 will induce mechanical stress at the material interfaces 7 . If vias are completely filled with Cu, then cracks in the Si can emerge during heating 8 .…”