3D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICs

Abstract

Abstract-3D Integrated Circuits (ICs) have been recently proposed as a solution to the increasing wire delay concerns in scaled technologies. At the same time, technology scaling leads to increasing variability in manufacturing process parameters, making it imperative to quantify the impact of these variations on performance. In this work, we take, to the best of our knowledge, the first step towards formally modeling the impact of process variations on the clock frequency of fully-synchronous (FS) 3D ICs. The proposed analytical models demonstrate theoretically and experimentally that 3D designs behave very differently under the impact of process variations as compared to equivalent 2D designs. In particular, for the same number of critical paths, we show that a 3D design is always less likely to meet a pre-defined frequency target compared to its 2D counterpart. Furthermore, as opposed to models for 2D ICs, the 3D models need to accurately account for not only within-die (WID) critical paths, i.e., paths that lie entirely within one of the die layers, but also D2D critical paths that use throughsilicon vias (TSVs) to span across multiple dies in the 3D stack. Finally, we show, theoretically and experimentally, that the mapping of critical paths to the die layers of a 3D IC can also affect the timing yield of a design, while the mapping issue does not arise in the 2D case since there is only a single die layer in a 2D IC. The accuracy of the proposed models is experimentally verified and found to be in excellent agreement with detailed SPICE and gate-level Monte Carlo (MC) simulations.

Post Silicon Management of On-Package Variation Induced 3D Clock Skew

“…As a result, dieto-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path [1][2][3]. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies.…”

“…They also provided detail analysis to show low power clocking property of the multi-TSV approach compared to the single-TSV approach in the work [8]. Kim and Kim proposed low cost and low power 3D CTS solution while guaranteeing a minimal use of TSVs in the work [9] and Manuscript received Aug. 22, 2011; revised Dec. 1,2011. School of Electrical Engineering and Computer Science, Seoul National University, Seoul, Korea E-mail : {takyung, tkim}@ssl.snu.ac.kr a non-zero skew bounded 3D clock tree routing algorithm in the work [10].…”

“…Importantly, the aforementioned 3D yield improvement works [16][17][18] did not consider different timing behavior of the 3D clock network compared to the 2D one. Moreover, 3D yield analysis works in [1][2][3] using the averaging effect of variation on data path can be more meaningful when we guarantee correct clock signal arrival under a tolerable 3D clock skew budget.…”

Skew variability in 3-D ICs with multiple clock domains

“…The variations of the gate length (lmos) of both the NMOS and PMOS are considered [14]. Other sources of variations can also be A clock tree of Scheme (A) is simulated through SPICE.…”

“…Since the planes of a 3-D IC are usually fabricated separately, the inter-die process variations are considered independent from plane to plane and uniform for the devices within one plane [14]. For a clock tree spanning N planes, the distribution of the skew S1,2 between sinks s1 and s2 considering inter-die (die-to-die (D2D)) variations is described by a Gaussian distribution [5],…”