3D GaN nanoarchitecture for field-effect transistors

Fatahilah, Muhammad Fahlesa; Strempel, Klaas; Feng, Yuqing; Vodapally, Sindhuri; Waag, A.; Wasisto, Hutomo Suryo

doi:10.1016/j.mne.2019.04.001

Cited by 37 publications

(35 citation statements)

References 121 publications

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“…Group III-nitride nanorods/nanowires (NWs) and nanowalls/ nanons (NFs) are expected to be applied in photo-catalysis, [1][2][3] sensing devices, [4][5][6][7] optoelectronics, [8][9][10][11][12][13][14] and high-power electronics. [15][16][17][18][19][20] In particular, selectively grown GaN nanostructures (NSs) benet from outstanding structural quality, e.g., due to strain relaxation and dislocation ltering, [21][22][23][24] making them a promising candidate for next-generation three-dimensional GaN-based NW/NF eld-effect transistors (NWFETs/FinFETs). Nevertheless, GaN-based high-electron-mobility transistors (HEMTs) suffer from self-heating during high-frequency and high-voltage operation leading to device damage.…”

Section: Introductionmentioning

confidence: 99%

Selective area growth of GaN nanowires and nanofins by molecular beam epitaxy on heteroepitaxial diamond (001) substrates

et al. 2021

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Section: Introductionmentioning

confidence: 99%

Selective area growth of GaN nanowires and nanofins by molecular beam epitaxy on heteroepitaxial diamond (001) substrates

et al. 2021

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“…Several solutions can be proposed to enhance the g m , including by decreasing L and increasing the W (i.e., shorter gate channel and larger NW diameter), as well as choosing the proper channel doping concentration design with the purpose of further increasing the electron mobility ( µ ) in p -channel to lower the scattering rate 48 . Review on vertical 3D GaN NW FETs including their important parameters to evaluate the device performances has been recently published elsewhere 25 .…”

Section: Resultsmentioning

confidence: 99%

“…In quantum engineered transistors and logic applications, this vertical method also gives a new strategy towards higher performance and integration of p - and n -channel transistors 17,18 . From our point of view, the vertical 3D architecture has become more attractive because it provides more advantages: (1) it can minimize the current collapse, thanks to the absence of surface-related trapping phenomena; (2) the gate length ( L ) is not limited by lithography process; (3) gating technology can be flexibly designed (e.g., wrap around gate); (4) vertical parallel current paths and collection can be obtained on a small footprint for high scalability; (5) better thermal performance, at which the maximum temperature is close to top part of NWs, brought potential to achieve more power density; and (6) contrary to lateral devices, where breakdown voltage scales with area (and cost), in vertical devices the breakdown voltage is only dependent on the thickness/properties of the epitaxial stacks 13,19–25 .…”

Section: Introductionmentioning

confidence: 99%

Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

Fatahilah

Feng

Strempel

et al. 2019

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This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1–100) and diameters (i.e., 220–640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p -channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage ( V th ) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al 2 O 3 ) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep V th shift (Δ V th ) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics.

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“…DEP can overcome such issues since the process is less destructive and requires no manual effort. For example, it is used in the assembly of single GaAs nanowires (NWs) for photodetectors [15] and in GaN nanoarchitecture assembly for field-effect transistors [16]. In our previous work, we utilized the DEP technique to place SrTiO 3 nanoparticles between two electrodes and measure their electrical properties [17].…”

Section: Introductionmentioning

confidence: 99%

Wirelessly powered dielectrophoresis of metal oxide particles using spark‐gap Tesla coil

et al. 2020

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Wirelessly powered dielectrophoresis (DEP) of metal oxide particles was performed using a spark‐gap Tesla coil (TC). The main contribution of this work is the simplification of the conventional DEP setup that requires attaching wires directly to the electrodes. Wireless power from the TC generates a high output frequency and voltage, which corresponds to that used for the DEP. Therefore, a spark‐gap TC was built and utilized to conduct the DEP process. Metal oxides (ZnO and Fe2O3) were used as targets for the assembly. The results showed that the wirelessly powered DEP technique via a TC was successful in assembling the metal oxide particles. Positive and negative DEP phenomena were observed. Positive DEP occurred during ZnO assembly, making particles chain grow 0.92 mm toward the sparks within 60 s. Negative DEP was observed during Fe2O3 assembly, where the repulsion of particles formed a void around the sparks with a 1.45 mm radius. The mechanism of this wireless DEP system is discussed.

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3D GaN nanoarchitecture for field-effect transistors

Cited by 37 publications

References 121 publications

Selective area growth of GaN nanowires and nanofins by molecular beam epitaxy on heteroepitaxial diamond (001) substrates

Selective area growth of GaN nanowires and nanofins by molecular beam epitaxy on heteroepitaxial diamond (001) substrates

Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

Wirelessly powered dielectrophoresis of metal oxide particles using spark‐gap Tesla coil

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