33.2 A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing

Liu, Qi; Gao, Bin; Yao, Peng; Wu, Dong; Chen, Junren; Pang, Yongqiang; Zhang, Wenqiang; Liao, Yehong; Xue, Cheng-Xin; Chen, Wei-Hao; Tang, Jianshi; Wang, Yu; Chang, Meng‐Fan; Qian, He; Wu, Huaqiang

doi:10.1109/isscc19947.2020.9062953

Cited by 167 publications

(85 citation statements)

References 2 publications

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“…Using a single nanoscale PCM device to represent each component of a 512-bit vector leads to a very high density key memory. The key memory can also be realized using other forms of in-memory computing based on resistive random access memory 33 or even charge-based approaches 34 . There are also several avenues to improve the efficiency of the controller.…”

Section: Resultsmentioning

confidence: 99%

Robust high-dimensional memory-augmented neural networks

et al. 2021

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Traditional neural networks require enormous amounts of data to build their complex mappings during a slow training procedure that hinders their abilities for relearning and adapting to new data. Memory-augmented neural networks enhance neural networks with an explicit memory to overcome these issues. Access to this explicit memory, however, occurs via soft read and write operations involving every individual memory entry, resulting in a bottleneck when implemented using the conventional von Neumann computer architecture. To overcome this bottleneck, we propose a robust architecture that employs a computational memory unit as the explicit memory performing analog in-memory computation on high-dimensional (HD) vectors, while closely matching 32-bit software-equivalent accuracy. This is achieved by a content-based attention mechanism that represents unrelated items in the computational memory with uncorrelated HD vectors, whose real-valued components can be readily approximated by binary, or bipolar components. Experimental results demonstrate the efficacy of our approach on few-shot image classification tasks on the Omniglot dataset using more than 256,000 phase-change memory devices. Our approach effectively merges the richness of deep neural network representations with HD computing that paves the way for robust vector-symbolic manipulations applicable in reasoning, fusion, and compression.

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Section: Resultsmentioning

confidence: 99%

Robust high-dimensional memory-augmented neural networks

et al. 2021

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“…Although the macro can perform a convolutional neural network (CNN) with very low latency, the output of the memristor cell is only 1 bit which largely limits its performance. In 2020, a 160 kb memristor chip with a 2T2R active array was proposed [71], where 3-bit signed weight was used in one memristor cell. The chip is fully integrated for a complete multi-layer ANN and achieves 78.4 TOPS/W peak energy efficiency and 94.4% test accuracy in the MNIST dataset.…”

Section: Ai Chipmentioning

confidence: 99%

Recent progress of integrated circuits and optoelectronic chips

Xiang

Han

Zhang

et al. 2021

Sci. China Inf. Sci.

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Integrated circuits (ICs) and optoelectronic chips are the foundation stones of the modern information society. The IC industry has been driven by the so-called "Moore's law" in the past 60 years, and now has entered the post Moore's law era. In this paper, we review the recent progress of ICs and optoelectronic chips. The research status, technical challenges and development trend of devices, chips and integrated technologies of typical IC and optoelectronic chips are focused on. The main contents include the development law of IC and optoelectronic chip technology, the IC design and processing technology, emerging memory and chip architecture, brain-like chip structure and its mechanism, heterogeneous integration, quantum chip technology, silicon photonics chip technology, integrated microwave photonic chip, and optoelectronic hybrid integrated chip.

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“…Typically, the synaptic weights in a neural network have a differential structure, thus two separate 1T1R memory devices are used for representing a single weight. This is shown in Figure 12a where two contiguous columns are used for representing positive and negative weights that are summed up in the digital domain [69]. This configuration results in a relatively large impact of the IR drop since two array locations are used for each matrix entry.…”

Section: Array-level Reliability Issuesmentioning

confidence: 99%

“…This configuration results in a relatively large impact of the IR drop since two array locations are used for each matrix entry. To mitigate this issues, Figure 12b shows a signed-weighted 2-transistor/2-resistor (SW-2T2R) structure to represent the positive and negative part of each weight, where the current summation is performed directly within the memory cell, thus effectively reducing the impact of IR drop by roughly a factor 2 [69]. Another approach is to use small-size crosspoint arrays and/or organize the IMC architecture in computing tiles [70,71], where the overall problem is divided in smaller operations with smaller summation currents, hence a lower IR drop.…”

Section: Array-level Reliability Issuesmentioning

confidence: 99%

In-Memory Computing with Resistive Memory Circuits: Status and Outlook

Pedretti

Ielmini

2021

Electronics

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In-memory computing (IMC) refers to non-von Neumann architectures where data are processed in situ within the memory by taking advantage of physical laws. Among the memory devices that have been considered for IMC, the resistive switching memory (RRAM), also known as memristor, is one of the most promising technologies due to its relatively easy integration and scaling. RRAM devices have been explored for both memory and IMC applications, such as neural network accelerators and neuromorphic processors. This work presents the status and outlook on the RRAM for analog computing, where the precision of the encoded coefficients, such as the synaptic weights of a neural network, is one of the key requirements. We show the experimental study of the cycle-to-cycle variation of set and reset processes for HfO2-based RRAM, which indicate that gate-controlled pulses present the least variation in conductance. Assuming a constant variation of conductance σG, we then evaluate and compare various mapping schemes, including multilevel, binary, unary, redundant and slicing techniques. We present analytical formulas for the standard deviation of the conductance and the maximum number of bits that still satisfies a given maximum error. Finally, we discuss RRAM performance for various analog computing tasks compared to other computational memory devices. RRAM appears as one of the most promising devices in terms of scaling, accuracy and low-current operation.

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33.2 A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing

Cited by 167 publications

References 2 publications

Robust high-dimensional memory-augmented neural networks

Robust high-dimensional memory-augmented neural networks

Recent progress of integrated circuits and optoelectronic chips

In-Memory Computing with Resistive Memory Circuits: Status and Outlook

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