Recent progress of integrated circuits and optoelectronic chips

Xiang, Shuiying; Han, Genquan; Zhang, Jincheng; Ma, Xiaohua; Zhu, Zhangming; Guo, Xingxing; Zhang, Yahui; Han, Yanan; Song, Ziwei; Liu, Yan; Yang, Ling; Zhou, Hong; Shi, Jiangyi; Zhang, Wei; Xu, Min; Zhao, Weisheng; Pan, Biao; Huang, Yangqi; Liu, Qi; Cai, Yimao; Zhu, Jiang; Ou, Xin; You, Tiangui; Wu, Huaqiang; Gao, Bin; Zhang, Zhiyong; Guo, Guo-Ping; Chen, Yonghua; Liu, Yong; Chen, Xiangfei; Xue, Chunlai; Wang, Xingjun; Zhao, Lianfeng; Zou, Xihua; Yan, Lianshan; Li, Ming

doi:10.1007/s11432-021-3235-7

Cited by 60 publications

(17 citation statements)

References 226 publications

(238 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is similar to the process of input spike routing. Darwin Chip's NPU is an SNN-based neuromorphic coprocessor, while it still is a single-chip system, for now, the standard communication interface defined by the AER format allows expanding to multi-chip distributed systems (Nejad, 2020;Cui et al, 2021;Hao et al, 2021;Ding et al, 2022) with AER bus connections in the future. NPU, as a processing element in a network-on-a-chip (NoC) architecture200, can use the AER format for input and output peaking to scale the SNN's size of the chip to potentially millions of neurons, not just thousands of neurons.…”

Section: Internal Spike Routingmentioning

confidence: 99%

An overview of brain-like computing: Architecture, applications, and future trends

Xiao²,

Zhu³

et al. 2022

Front. Neurorobot.

View full text Add to dashboard Cite

With the development of technology, Moore's law will come to an end, and scientists are trying to find a new way out in brain-like computing. But we still know very little about how the brain works. At the present stage of research, brain-like models are all structured to mimic the brain in order to achieve some of the brain's functions, and then continue to improve the theories and models. This article summarizes the important progress and status of brain-like computing, summarizes the generally accepted and feasible brain-like computing models, introduces, analyzes, and compares the more mature brain-like computing chips, outlines the attempts and challenges of brain-like computing applications at this stage, and looks forward to the future development of brain-like computing. It is hoped that the summarized results will help relevant researchers and practitioners to quickly grasp the research progress in the field of brain-like computing and acquire the application methods and related knowledge in this field.

show abstract

Section: Internal Spike Routingmentioning

confidence: 99%

An overview of brain-like computing: Architecture, applications, and future trends

Xiao²,

Zhu³

et al. 2022

Front. Neurorobot.

View full text Add to dashboard Cite

show abstract

“…The use of CNT channel material in a FET structure is considered to be a candidate approach to achieve lowpower, high-performance next-generation technology. To date, many circuit simulations [32][33][34], high-frequency applications [35], as well as fabrication-based studies on CNFET-based circuits [36][37][38][39][40][41] have been reported. Recent works on CNFET-based digital applications include the integration of logic gates and memory unis for microprocessor development [41].…”

Section: The Cnfet-based Design Of the 2 × 2 Binary Multipliermentioning

confidence: 99%

The design and performance of different nanoelectronic binary multipliers

Ghosh¹,

Jain

Sarkar

2021

J Comput Electron

View full text Add to dashboard Cite

The design and performance of digital binary multipliers built using different types of nanoelectronic devices are investigated herein. Designs for 2 × 2 binary multipliers implemented using different technologies such as single-electron-threshold logic (SE-TLG), hybrid single-electron transistor/complementary metal-oxide-semiconductor (SET-CMOS), and carbon nanotube field-effect transistor (CNFET) devices are elaborated and presented with corresponding simulation results. The performance metrics considered for their comparison are the power consumption, the circuit area, the propagation delay, the operating temperature, the design platform, etc. The existing CMOS-based design is also compared with all three proposed designs. The comparative analysis indicates that the SE-TLG-based 2 × 2 binary multiplier design exhibits very low power consumption, the smallest area requirement, and the shortest propagation delay among the three. Meanwhile, the design based on hybrid SET-CMOS devices can operate at room temperature and delivers the optimal response in terms of all the other performance metrics when compared with the other circuit implementations considered herein. Further stability analysis of the designs based on SE-TLG and hybrid SET-CMOS devices is carried out to validate their performance.

show abstract

“…The massive amount of data movement generated by application-driven traffic demand such as HD video streaming, cloud-based computing and storage, Internet-of-Things, and 5G applications is forecasted to reach 28.8 zettabytes by 2022, and it will grow at a compound average rate of 30% per year. To meet this demand, innovations of interconnect are urgently needed to provide denser connectivity with high bandwidth, low latency, and high energy efficiency in a cost-effective manner, especially in the datacenters and high-performance computing systems [1,2]. Optical interconnects are emerging as a viable solution over copper wires for board-to-board data communication [3].…”

Section: Introductionmentioning

confidence: 99%

Numerical Demonstration of 800 Gbps WDM Silicon Photonic Transmitter with Sub-Decibel Surface-Normal Optical Interfaces

Zhang

et al. 2022

Micromachines

View full text Add to dashboard Cite

We propose and numerically demonstrate an 800 Gbps silicon photonic transmitter with sub-decibel surface-normal optical interfaces. The silicon photonic transmitter is composed of eight silicon Mach–Zehnder optical modulators and an interleaved AMMI WDM device. This WDM device comprises two 1 × 4 angled MMI and a Mach–Zehnder interferometer (MZI) optical interleaver with an apodized bidirectional grating which has about −0.5 dB coupling loss. Both the Mach–Zehnder electro-optical modulators and MZI optical interleaver regard the bidirectional grating coupler as vertical optical coupler and 3-dB power splitter/combiner. By importing the S-parameter matrices of all the components which have been carefully designed in simulation software, the circuit-level model of the optical transmitter can be built up. On this basis, the static and dynamic performance characterization were carried out numerically. For NRZ modulation, the optical transmitter exhibits the overall optical loss of 4.86–6.72 dB for eight wavelength channels. For PAM4 modulation, the optical loss is about 0.5 dB larger than that of NRZ modulation, which varies between 5.38–7.27 dB. From the eye diagram test results, the WDM silicon photonic transmitter can achieve single channel data transmission at 100 Gb/s NRZ data or 50 GBaud/s PAM4 symbol rate with acceptable bit error rate.

show abstract

Recent progress of integrated circuits and optoelectronic chips

Cited by 60 publications

References 226 publications

An overview of brain-like computing: Architecture, applications, and future trends

An overview of brain-like computing: Architecture, applications, and future trends

The design and performance of different nanoelectronic binary multipliers

Numerical Demonstration of 800 Gbps WDM Silicon Photonic Transmitter with Sub-Decibel Surface-Normal Optical Interfaces

Contact Info

Product

Resources

About