300mm Full Thickness Si-Based IC Singulation Using Plasma Dicing for Advanced Packaging Technologies

Surapaneni, R.; Hamlin, B. S.; Chiu, Julia J.; Brun, Xavier F.; Barnett, Richard; Muggeridge, M.; Bhasker, H.; Richards, N.

doi:10.1109/ectc51906.2022.00166

Cited by 2 publications

(2 citation statements)

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“…In addition, 29,251 dies of 1 mm 2 size were obtained from 200 mm diameter wafers using plasma dicing, showing a more efficient method than mechanical dicing (24,867 dies) and laser dicing (26,798 dies). A 775 µm thick Si wafer with a HAR of 13:1 and 20:1 has been attained utilizing plasma dicing [81]. They also showed how the process and sidewall quality for plasma dicing affected the die break strength at various orientations and presented a comparison of sidewall quality and process timings to traditional mechanical blade dicing for certain die sizes.…”

Section: Plasma Dicing Of Si-wafer With Tsvsmentioning

confidence: 99%

“…Plasma dicing produces fewer chippings after cutting and does not cause physical damage compared to mechanical or laser dicing. Thus, it demonstrates a better die quality and economy, which is suitable for dicing thin wafers [81][82][83]. Figure 3 shows a 300 mm plasma-diced silicon wafer plated with −7 to −10 mA/cm 2 for 2.5 h [80].…”

Section: Plasma Dicing Of Si-wafer With Tsvsmentioning

confidence: 99%

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Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

Jang,

Sharma,

Jung

2023

Materials

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Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for achieving high-density integration, high-speed connectivity, and for downsizing of electronic devices. This paper describes recent developments in TSV fabrication and bonding methods in advanced 3D electronic packaging. In particular, the authors have overviewed the recent progress in the fabrication of TSV, various etching and functional layers, and conductive filling of TSVs, as well as bonding materials such as low-temperature nano-modified solders, transient liquid phase (TLP) bonding, Cu pillars, composite hybrids, and bump-free bonding, as well as the role of emerging high entropy alloy (HEA) solders in 3D microelectronic packaging. This paper serves as a guideline enumerating the current developments in 3D packaging that allow Si semiconductors to deliver improved performance and power efficiency.

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Section: Plasma Dicing Of Si-wafer With Tsvsmentioning

confidence: 99%