30-ns 55-b shared radix 2 division and square root using a self-timed circuit

Matsubara, G.; Ide, N.; Tago, H.; Suzuki, Susumu; Goto, N.

doi:10.1109/arith.1995.465371

Cited by 11 publications

(10 citation statements)

References 8 publications

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“…But in the case of the division operation, only straightforward algorithms have been studied. Most of the previous works use a radix-2 SRT algorithm (with quotient digits in ¢ ¡ ¤ £ ¦ ¥ § © ¥ £ ) and a residual represented using a carry-save number system [10,11,12,13] or a borrow-save number system [14]. A recent high-radix approach [15] presents a speculative radix-64 or radix-128 SRT algorithm.…”

Section: Introductionmentioning

confidence: 99%

<title>On digit-recurrence division algorithms for self-timed circuits</title>

Boullis

Tisserand

2001

Advanced Signal Processing Algorithms, Architectures, and Implementations XI

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To cite this version:Nicolas Boullis, Arnaud Tisserand. On digit-recurrence division algorithms for self-timed circuits.[ Abstract: The optimization of algorithms for self-timed or asynchronous circuits requires specific solutions. Due to the variable-time capabilities of asynchronous circuits, the average computation time should be optimized and not only the worst case of the signal propagation. If efficient algorithms and implementations are known for asynchronous addition and multiplication, only straightforward algorithms have been studied for division. This paper compares several digit-recurrence division algorithms (speed, area and circuit activity for estimating the power consumption). The comparison is based on simulations of the different operators described at the gate level. This work shows that the best solutions for asynchronous circuits are quite different from those used in synchronous circuits. Key-words:Computer arithmetic, division algorithms, SRT tables, asynchronous circuits, self-timed circuits Algorithmes de division chiffres à chiffres pour les circuits asynchronesRésumé : L'optimisation des algorithmes pour les circuits asynchrones nécessite des solutions spécifiques. Du fait des capacités de calcul en temps variable des circuits asynchrones, le temps moyen de calcul doit être optimisé et plus seulement le temps du pire cas. Si de bons algorithmes et des implantations efficaces sont connus pour l'addition et la multiplication asynchrones, seules des solutions simplistes ont été étudiées pour la division. Ce papier compare plusieurs algorithmes de division basés sur des récurrences sur les chiffres du quotient (les critères de comparaison sont la vitesse, la surface et la consommationn d'énergie). Cette comparaison est basée sur des simulations au niveau des portes logiques. Ce travail montre que les meilleures solutions pour les circuits asynchrones sont véritablement différentes de celles admises pour les circuits synchrones.

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Section: Introductionmentioning

confidence: 99%

<title>On digit-recurrence division algorithms for self-timed circuits</title>

Boullis

Tisserand

2001

Advanced Signal Processing Algorithms, Architectures, and Implementations XI

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“…This calculation time of 16Ons is almost the same as other synchronous implementation using 0.5 ,U m CMOS technology [7]. In our previous work [3], the zerooverhead scheme also showed a very fast calculation, 2.5 times as fast as the synchronous implementation in a shared division and square root unit.…”

Section: Combination Of Single-rail and Dual-rail Circuitsmentioning

confidence: 73%

“…As aresult, the shared division and square root unit required 22-b wires for a 1-b portion of the 55-b calculation unit in our previous study [3]. If the total width of the calculation unit is 1.…”

Section: Introductionmentioning

confidence: 97%

“…The automatically provided reset and set-up signals to the dynamic circuit stages by using the completion signals can make the circuit zero-overhead that means the precharging (reset) time is completely removed from the calculation time [l]. The comparison between the zerooverhead self-timed implementation and a clock-based static circuit implementation showed that the calculation time for a 55-b division or a square root was shortened by 2.5 times [3]. In contrast to the high speed calculation, the zerooverhead circuit has disadvantages in power consumption and layout area for wiring.…”

Section: Introductionmentioning

confidence: 99%

“…A zero-overhead self-timed circuit [l] consists of a dynamic differential cascode voltage switch logic (DCVSL) circuit [2] can make a very fast division and square root unit [3] using an iterative calculation algorithm. This technique is based on dual-rail wiring in which both signal value and timing are encoded as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

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A low power zero-overhead self-timed division and square root unit combining a single-rail static circuit with a dual-rail dynamic circuit

Matsubara

Ide²

Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems

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An asynchronous pipeline scheme that combines a low power static circuit with a high-speed dual-rail dynamic circuit is proposed. The scheme utilizes a dual-rail circuit only in the critical path of an SRT division and square root calculation unit. The proposed implementation of the calculation unit reduced power consumption by more than 112 of the full-dynamic implementation while maintaining the calculation speed. Because of the elimination of spurious transitions, the proposed implementation showed even less power consumption over synchronous static circuit implementations. By using 0.3 , U m triple metal CMOS technology, the calculation time of floating point 56-b full mantissa division and square root is expected to be 45ns in the worst case.

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Square Root by Digit Recurrence

Ercegovac¹,

Lang²

2004

Digital Arithmetic

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30-ns 55-b shared radix 2 division and square root using a self-timed circuit

Cited by 11 publications

References 8 publications

<title>On digit-recurrence division algorithms for self-timed circuits</title>

<title>On digit-recurrence division algorithms for self-timed circuits</title>

A low power zero-overhead self-timed division and square root unit combining a single-rail static circuit with a dual-rail dynamic circuit

Square Root by Digit Recurrence

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