30.2 A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm<sup>2</sup> Bit Density

Khakifirooz, A.; Balasubrahmanyam, S.; Fastow, R.; Gaewsky, Kristopher H.; Ha, Changwan; Haque, Rezaul; Jungroth, O.; Law, S.M.; Madraswala, Aliasgar S.; Ngo, Binh; Prabhu, Naveen; Rajwade, Shantanu; Ramamurthi, K.; Shenoy, Rohit S.; Snyder, Julie; Sun, Cindy; Thimmegowda, Deepak; Pathak, B.; Kalavade, P.

doi:10.1109/isscc42613.2021.9365777

Cited by 28 publications

(9 citation statements)

References 5 publications

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“…Given that the block size is the minimum granularity of erase, the increase in the block size could increase the system burden of the data management and would degrade system performance. In order to mitigate this problem, the block-by-deck scheme was proposed (Figure 23b) [30]. In this scheme, the NAND string is divided into multiple segments (three segments in this example) and each segment is treated as a different block.…”

Section: Block Size Scalingmentioning

confidence: 99%

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Recent Progress on 3D NAND Flash Technologies

Goda

2021

Electronics

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Since 3D NAND was introduced to the industry with 24 layers, the areal density has been successfully increased more than ten times, and has exceeded 10 Gb/mm2 with 176 layers. The physical scaling of XYZ dimensions including layer stacking and footprint scaling enabled the density scaling. Logical scaling has been successfully realized, too. TLC (triple-level cell, 3 bits per cell) is now the mainstream in 3D NAND, while QLC (quad-level cell, 4 bits per cell) is increasing the presence. Several attempts and partial demonstrations were made for PLC (penta-level cell, 5 bits per cell). CMOS under array (CuA) enabled the die size reduction and performance improvements. Program and erase schemes to address the technology challenges such as short-term data retention of the charge-trap cell and the large block size are being investigated.

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Section: Block Size Scalingmentioning

confidence: 99%

“…In this way, the cells in the unselected deck blocks can be inhib- In the FG NAND, the first programming pass only has four levels. The 16 levels are then completed at the second pass [30] because the short-term retention is much smaller in the FG cell and does not require the touch-up operation.…”

Section: Block Size Scalingmentioning

confidence: 99%

Recent Progress on 3D NAND Flash Technologies

Goda

2021

Electronics

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“…2 Moreover, by storing multiple bits in three-dimensionally integrated memory cells, the limitation of in-plane scaling has been overcome, along with reduction in cost per bit. [3][4][5][6][7] Owing to such remarkable technological advances, flash memory has been extensively used as primary storage, from memory cards to data centers, and is also a viable choice as a primitive cell for in-memory computing architecture. [8][9][10][11] The concept of in-memory computing can dramatically reduce data-transferring energy between memory and computing units by performing most computations in the memory device array.…”

Section: Introductionmentioning

confidence: 99%

“…Consequently, the physical dimensions of flash memory devices have drastically shrunk down (10 nm level), with their memory capacity increased to hundreds of gigabits in a chip without any reliability penalty 2 . Moreover, by storing multiple bits in three‐dimensionally integrated memory cells, the limitation of in‐plane scaling has been overcome, along with reduction in cost per bit 3–7 . Owing to such remarkable technological advances, flash memory has been extensively used as primary storage, from memory cards to data centers, and is also a viable choice as a primitive cell for in‐memory computing architecture 8–11 .…”

Section: Introductionmentioning

confidence: 99%

Ferro‐floating memory: Dual‐mode ferroelectric floating memory and its application to in‐memory computing

Park

Lee

et al. 2022

InfoMat

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Various core memory devices have been proposed for utilization in future in‐memory computing technology featuring high energy efficiency. Flash memory is considered as a viable choice owing to its high integration density, stability, and reliability, which has been verified by commercialized products. However, its high operating voltage and slow operation speed issues caused by the tunneling mechanism make its adoption in in‐memory computing applications difficult. In this paper, we introduce a dual‐mode memory device named “ferro‐floating memory”, fabricated using van der Waals (vdW) materials (h‐BN, MoS2, and α‐In2Se3). The vdW material, α‐In2Se3, acts as a polarization control layer for the ferroelectric memory operation and charge storage layer for the conventional flash memory operation. Compared to the tunneling‐based memory operation, the ferro‐floating memory operates 1.9 and 3.3 times faster at 6.7 and 5.8 times lower operating voltages for programming and erasing operations, respectively. The dual‐mode operation improves the linearity of conductance change by 5 times and the dynamic range by 48% through achieving conductance variation regions. Furthermore, we assess the effects of the variation in device operating voltage on neural networks and suggest a memory array operating scheme for maximizing the networks' performance through various training/inference simulations.

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“…Nowadays, NAND Flash memory is widely used in mass storage applications. Threedimensional NAND Flash memory with 3D stacked IC (SIC) [17,18] is the most viable solution for high-capacity storage and low-bit-cost non-volatile memory [19,20]. During the contact-type usage, the pins of packaged die may be exposed to ESD sources such as human fingers; hence, ESD immunity is required for NAND Flash memory.…”

Section: Introductionmentioning

confidence: 99%

Analysis of HBM Failure in 3D NAND Flash Memory

Song

Li²,

Wang³

et al. 2022

Electronics

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Electrostatic discharge (ESD) events are the main factors impacting the reliability of NAND Flash memory. The behavior of human body model (HBM) failure and the corresponding physical mechanism of 3D NAND Flash memory are investigated in this paper. A catastrophic burn-out failure during HBM zapping is first presented. Analysis shows that NMOS fingers’ local heating induced by inhomogeneous substrate resistance Rsub and local heating induced by the drain contact and 3D stacked IC (SIC) structure lead to the failure. Therefore, a new approach is proposed to reduce local heat generation. Finally, by increasing N+ length (NPL) and introducing a novel contact strip, the silicon result shows enhanced ESD robustness.

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30.2 A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm² Bit Density

Cited by 28 publications

References 5 publications

Recent Progress on 3D NAND Flash Technologies

Recent Progress on 3D NAND Flash Technologies

Ferro‐floating memory: Dual‐mode ferroelectric floating memory and its application to in‐memory computing

Analysis of HBM Failure in 3D NAND Flash Memory

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30.2 A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm2 Bit Density

Cited by 28 publications

References 5 publications

Recent Progress on 3D NAND Flash Technologies

Recent Progress on 3D NAND Flash Technologies

Ferro‐floating memory: Dual‐mode ferroelectric floating memory and its application to in‐memory computing

Analysis of HBM Failure in 3D NAND Flash Memory

Contact Info

Product

Resources

About

30.2 A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm² Bit Density