3-D electrothermal simulation of active cycling on smart power MOSFETs during short-circuit and UIS conditions

Riccio, Michele; d’Alessandro, V.; Irace, Andrea; Rostaing, Gilles; Berkani, Mounira; Lefebvre, Stéphane; Dupuy, Philippe

doi:10.1016/j.microrel.2014.08.011

Cited by 2 publications

(1 citation statement)

References 15 publications

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“…3) For the purpose of entire-device simulation of reliability issues, some electrothermal analysis methods have been proposed. 6,8,10,[14][15][16][17][18][19][20][21] They are based on electrothermal circuit simulation or theoretical calculation. For example, the change of the three-dimensional distribution of the internal temperature or the maximum energy stored in the load can be analyzed.…”

Section: Introductionmentioning

confidence: 99%

An electrothermal compact model of SiC MOSFETs for analyzing avalanche failure mechanisms

Shimozato

Nakamura

Bian

et al. 2021

Jpn. J. Appl. Phys.

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Avalanche failure that occurs in circuits with inductive loads is an important issue facing silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs). Two mechanisms have been suggested for this failure: the activation of a parasitic bipolar junction transistor (BJT), and the intrinsic operation of SiC at extremely high temperatures. In this study, we propose a SPICE-based electrothermal simulation model of SiC MOSFETs to simulate avalanche behavior. The proposed compact MOSFET model includes a parasitic BJT, a body diode, and an intrinsic resistance. The intrinsic resistor represents the decreasing resistance of SiC due to its intrinsic operation in extremely high temperatures. The simulation results of our model accurately reproduce the measurement results of an unclamped inductive switching (UIS) test. According to the simulation results, the main cause of MOSFET failure in the UIS test is that SiC enters intrinsic operation because of the rapid increase of junction temperature over 1200 K.

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Section: Introductionmentioning

confidence: 99%

An electrothermal compact model of SiC MOSFETs for analyzing avalanche failure mechanisms

Shimozato

Nakamura

Bian

et al. 2021

Jpn. J. Appl. Phys.

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Surface analysis of smart power top metal: IR thermal measurement and source potential mapping

Berkani¹,

Lefebvre²,

Rostaing³

et al. 2016

2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD)

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Reliability of modern power MOSFETs is assessed through accelerated electro-thermal aging tests. Top metallization layer reconstruction is one of the most observed degradation mechanisms in power devices operating under short circuit conditions. Experimental analysis results focused on temperature measurement and source potential mapping during ageing will be presented to corroborate previous results on electrical parameters evolution and to give new tools for health monitoring. © 2016 IEEE

show abstract

3-D electrothermal simulation of active cycling on smart power MOSFETs during short-circuit and UIS conditions

Cited by 2 publications

References 15 publications

An electrothermal compact model of SiC MOSFETs for analyzing avalanche failure mechanisms

An electrothermal compact model of SiC MOSFETs for analyzing avalanche failure mechanisms

Surface analysis of smart power top metal: IR thermal measurement and source potential mapping

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