3.3 V, novel circuit techniques for a 2.8-million-transistor BiCMOS RISC processor

Yamauchi, Tsuyoshi; Iwamura, M.; Hotta, Takashi; Kobayashi, Y.; Nakano, T.; Mori, Kenichi; Shimizu, Tsuyoshi; Satomura, R.; Mitani, Seiji; Shiozawa, Kenji; Kitamura, N.; Yamagiwa, A.; Hayashi, Tsuyoshi

doi:10.1109/cicc.1993.590697

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A New Bicmos Adder3

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“…8(a) and (b) shows the propagation delay and the average power dissipation for different load capacitances. As depicted from the results, the new circuit outperforms [14] in terms of speed. The speed improvement is even more significant at higher loads.…”

Section: A New Bicmos Addermentioning

confidence: 83%

“…The speed improvement is even more significant at higher loads. However, the new circuit consumes slightly more power than [14]. The full-swing performance (not shown) of both circuits is sustained over a wide range of capacitance loadings.…”

Section: A New Bicmos Addermentioning

confidence: 99%

“…5. The new adder circuit is compared to [14] based on equal chip area and simulated for a ramp input of 200 ps rise time.…”

Section: A New Bicmos Addermentioning

confidence: 99%

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