3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor

Hotta, Takashi; Tanaka, S.; Yamauchi, Tsuyoshi; Yamada, H.; Nakano, T.; Kobayashi, Y.; Bandoh, T.

doi:10.1109/4.278351

Cited by 9 publications

(2 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Even though there are previously published comparator implementations [7] - [9], these architectures often only refer to the comparator without providing concrete design details. An exception for this is the design of combined two's complement and floating point comparator [4].…”

Section: Related Previous Workmentioning

confidence: 99%

A novel floating point comparator using parallel tree structure

Samuel

Senthilkumar

2015

2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]

View full text Add to dashboard Cite

In recent years, floating point numbers are widely adopted due to its good robustness against quantization errors and high dynamic range capabilities. In this paper, a novel single-precision floating point comparator design is proposed. A parallel prefix tree structure is literally the back bone of this comparator design. This is designed using Verilog code, simulated and synthesised using CADENCE ENCOUNTER tool with TSMC 180nm technology. The proposed comparator fully supports single precision floating-point comparisons, as defined in the IEEE 754 standard. The proposed floating point comparator design exploits the advantages of structural reusability. Cadence Encounter synthesis for a 32-b floating point comparator shows a worst case input-output delay of 3.014 ns and a total power dissipation of 91.8µW using 0.18-μm TSMC technology. The replacement of NOR-NAND gate using OR gate in the decision module incurs the improvement in the performance which thereby outperforms the existing design.Keywords-Floating point number, parallel prefix tree, IEEE 754 format.

show abstract

Section: Related Previous Workmentioning

confidence: 99%

A novel floating point comparator using parallel tree structure

Samuel

Senthilkumar

2015

2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]

View full text Add to dashboard Cite

show abstract

“…In order to realize a high-speed sense system, Ct and the amplitude of DV must be reduced. In this study, load reduction was attempted by the common emitter method, using devices with a small emitter junction area [4] and lowamplitude DV.…”

Section: Sense Systemmentioning

confidence: 99%