3.2 Zen: A next-generation high-performance ×86 core

Teja, Singh; Sundar, Rangarajan; John, Deepesh; Henrion, Carson; Southard, S.; McIntyre, H.; Novak, Amy; Kosonocky, Stephen; Jotwani, Ravi; Schaefer, Alex; Chang, Edward Yi; Bell, J. S.; Co, Michael

doi:10.1109/isscc.2017.7870256

Cited by 37 publications

(23 citation statements)

References 3 publications

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“…The processor consists of 2 Core Complexes (CCX). A CCX is a module containing 4 cores, which can connect to other CCX modules via Infinity Fabric [57], [58]. We did not observe extra conflicts other than the cache conflicts on this processor either.…”

Section: Attacking Amd Non-inclusive Cachesmentioning

confidence: 78%

Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World

Yan

Sprabery

Gopireddy

et al. 2019

2019 IEEE Symposium on Security and Privacy (SP)

120

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Although clouds have strong virtual memory isolation guarantees, cache attacks stemming from shared caches have proved to be a large security problem. However, despite the past effectiveness of cache attacks, their viability has recently been called into question on modern systems, due to trends in cache hierarchy design moving away from inclusive cache hierarchies.In this paper, we reverse engineer the structure of the directory in a sliced, non-inclusive cache hierarchy, and prove that the directory can be used to bootstrap conflict-based cache attacks on the last-level cache. We design the first cross-core Prime+Probe attack on non-inclusive caches. This attack works with minimal assumptions: the adversary does not need to share any virtual memory with the victim, nor run on the same processor core. We also show the first high-bandwidth Evict+Reload attack on the same hardware. We demonstrate both attacks by extracting key bits during RSA operations in GnuPG on a state-of-the-art non-inclusive Intel Skylake-X server.

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Section: Attacking Amd Non-inclusive Cachesmentioning

confidence: 78%

Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World

Yan

Sprabery

Gopireddy

et al. 2019

2019 IEEE Symposium on Security and Privacy (SP)

120

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“…L OW-Dropout (LDO) Regulators have been extensively used to achieve fine-grained power delivery and power management in system-on-chip (SoC) platforms having multiple voltage domains and various load circuits [1]- [5]. Their power delivery networks commonly have hierarchical structures as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

“…Due to these advantages, DLDOs have been commercially adopted in various SoCs already. For example, IBM in their 22-nm POWER8 processor [1] and AMD in their 14-nm RYZEN processor [5] integrated distributed DLDOs to achieve highly efficient fine-grained power management low supply voltages.…”

Section: Introductionmentioning

confidence: 99%

Architectural Advancement of Digital Low-Dropout Regulators

Akram

Hwang

2020

IEEE Access

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Digital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient finegrained power delivery and management in system-on-chips (SoCs) due to their process scalability, ease of integration, and low-voltage operation. However, conventional DLDOs suffer gravely from the power-speed tradeoff, which arises from the use of sampling clocks. To obtain reasonable performance in the undershoot and recovery during load transient states, a large output capacitor is inevitably required in these DLDOs. Moreover, they inherently involve large steady-state voltage ripples and poor power-supply rejection (PSR). These limitations of synchronous DLDOs and their counter measures are thoroughly discussed in this paper. Various design strategies of major building blocks, i.e. comparators and power transistor arrays, are explained in detail with examples. Architectural advances are also expounded including state-of-the-art DLDO architectures such as clock-boosted synchronous, analog-assisted synchronous, asynchornous, eventdriven, and hybrid DLDOs. These state-of-the-art DLDOs do not only address the power-speed tradeoff and achieve fast load transient responses, but also can eliminate the use of an output capacitor in some cases. Moreover, some hybrid DLDOs successfully removed the steady state ripples and achieve high PSR. All of these DLDO are compared on basis of their performance metrics and figure-of-merits (FOMs).

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“…Architecting an e cient power delivery network (PDN) for client processors (e.g., tablets, laptops, desktops) is a wellknown challenge that has been hotly debated in industry and academia in recent years. Due to multiple constraints, a modern client processor typically implements only one of three types of commonly-used PDNs: 1) motherboard voltage regulators (MBVR [29,41,63,97]), 2) low dropout voltage regulators (LDO [15,18,111,112,113,120]), and 3) integrated voltage regulators (IVR [21,61,88,117]). We nd that the energy-e ciency of each of the three di erent commonly-used PDN types varies di erently with the processor power (e.g., thermal design power (TDP 1 ) and dynamic power-state) and workload characteristics (e.g., workload type and computational intensity).…”

Section: Introductionmentioning

confidence: 99%

“…First, doing so allows system manufacturers to con gure a processor's TDP (known as con gurable TDP [5,63,132] or cTDP) to enable the processor to operate at higher or lower performance levels, depending on the available cooling capacity and desired power consumption. For example, the Intel Skylake processor uses an MBVR PDN [26,117] for all TDP ranges (from 3W [56] to 91W [57]) and recent AMD client processors use an LDO PDN [3,4,15,18,111,112], while enabling cTDP [56,57]. Second, it reduces non-recurring engineering (NRE [81]) cost and design complexity to allow competitive product prices and enable meeting of strict time-to-market requirements.…”

Section: Introductionmentioning

confidence: 99%

FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors

Haj-Yahya¹,

Alser²,

Kim³

et al. 2020

Preprint

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Modern client processors typically use one of three commonlyused power delivery network (PDN) architectures: 1) motherboard voltage regulators (MBVR), 2) integrated voltage regulators (IVR), and 3) low dropout voltage regulators (LDO). We observe that the energy-e ciency of each of these PDNs varies with the processor power (e.g., thermal design power (TDP) and dynamic power-state) and workload characteristics (e.g., workload type and computational intensity). This leads to energyine ciency and performance loss, as modern client processors operate across a wide spectrum of power consumption and execute a wide variety of workloads.To address this ine ciency, we propose FlexWatts, a hybrid adaptive PDN for modern client processors whose goal is to provide high energy-e ciency across the processor's wide range of power consumption and workloads. FlexWatts provides high energy-e ciency by intelligently and dynamically allocating PDNs to processor domains depending on the processor's power consumption and workload. FlexWatts is based on three key ideas. First, FlexWatts combines IVRs and LDOs in a novel way to share multiple on-chip and o -chip resources and thus reduce cost, as well as board and die area overheads. This hybrid PDN is allocated for processor domains with a wide power consumption range (e.g., CPU cores and graphics engines) and it dynamically switches between two modes: IVR-Mode and LDO-Mode, depending on the power consumption. Second, for all other processor domains (that have a low and narrow power range, e.g., the IO domain), FlexWatts statically allocates o -chip VRs, which have high energy-e ciency for low and narrow power ranges. Third, FlexWatts introduces a novel prediction algorithm that automatically switches the hybrid PDN to the mode (IVR-Mode or LDO-Mode) that is the most bene cial based on processor power consumption and workload characteristics.

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3.2 Zen: A next-generation high-performance ×86 core

Cited by 37 publications

References 3 publications

Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World

Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World

Architectural Advancement of Digital Low-Dropout Regulators

FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors

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