Architectural Advancement of Digital Low-Dropout Regulators

Abstract

Digital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient finegrained power delivery and management in system-on-chips (SoCs) due to their process scalability, ease of integration, and low-voltage operation. However, conventional DLDOs suffer gravely from the power-speed tradeoff, which arises from the use of sampling clocks. To obtain reasonable performance in the undershoot and recovery during load transient states, a large output capacitor is inevitably required in these DLDOs. Moreover, they inherently involve large steady-state voltage ripples and poor power-supply rejection (PSR). These limitations of synchronous DLDOs and their counter measures are thoroughly discussed in this paper. Various design strategies of major building blocks, i.e. comparators and power transistor arrays, are explained in detail with examples. Architectural advances are also expounded including state-of-the-art DLDO architectures such as clock-boosted synchronous, analog-assisted synchronous, asynchornous, eventdriven, and hybrid DLDOs. These state-of-the-art DLDOs do not only address the power-speed tradeoff and achieve fast load transient responses, but also can eliminate the use of an output capacitor in some cases. Moreover, some hybrid DLDOs successfully removed the steady state ripples and achieve high PSR. All of these DLDO are compared on basis of their performance metrics and figure-of-merits (FOMs).

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

“…The power loss from the resistive division increases as the dropout voltage increases [3], [45]. The power efficiency of a LDO is directly related to the dropout voltage as follows:…”

“…To utilize the advantages of buck and LDO converters simultaneously, a heterogeneous PDN is commonly adopted [11], [12], [19], [20], [22], [24], [45], [49], [50]. As illustrated in Fig.…”

“…As shown, the boosted clock significantly reduces the peak of voltage undershoot ∆ V REG and the transient response time (T R ) by shortening the feedback loop response time (t RES ). It is because the peak of ∆ V REG mainly depends on the t RES with a given load current step ∆ I LOAD and the output capacitor (C L ) [45]. ∆V REG can be roughly calculated as follows:…”

Evaluation and Perspective of Analog Low-Dropout Voltage Regulators: A Review

“…The LDOs used in PMICs and PMUs can be categorized into DLDOs, ALDOs, and hybrid LDOs, which combine analog and digital LDOs within the control circuit. Compared to ALDOs, DLDOs can perform better under low-voltage conditions as they do not suffer in stability with incurred compensation issues and it is processed scalable [19]. However, the bottleneck due to power supply rejection (PSR) and output voltage ripple remains the key design challenge in DLDOs [18].…”

“…However, the bottleneck due to power supply rejection (PSR) and output voltage ripple remains the key design challenge in DLDOs [18]. Furthermore, the requirement for a clock signal in DLDOs gives an additional challenge in terms of reducing the current consumption or the quiescent current of a DLDO and consequently limits efforts to improve its efficiency [19], [20]. ALDOs exhibit better performance in terms of voltage ripple and superior PSR compared to DLDOs [20], although continuous process scaling resulting in chip area downsizing and the reduction or elimination of external components present new design challenges for ALDOs [21].…”