3.2 multi-standard 185fs<inf>rms</inf> 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS

Abstract

As processing and network speeds are accelerated to support data-rich services, the bandwidth of backplane interconnects needs to be increased while maintaining the channel length and multi-rate links. However, channel losses and impedance discontinuities increase at high data-rates, making it difficult to compensate the channel. In this work, we target serial links from autonegotiation in 100G-KR4 of 0.3Gb/s to 32GFC of 28.05Gb/s in 40dB backplane architecture [1][2][3]. To achieve this challenge, there are two key techniques. First, we introduce a 36-tap decision-feedback equalizer (DFE) to cancel reflections due to connectors because these reflections close the eye. To operate the 36-tap DFE, we need to fix a CDR lock-point and calculate 36-tap coefficients accurately. Thus, we develop a pattern-captured CDR with a 4b pattern filter to fix the lock-point, and a 3b pattern-matched adaptive equalizer (AEQ) to optimize 36 tap coefficients. These techniques enable our chip to compensate 40dB channel loss. Second, we target 100G-KR4/40G-KR4/10G-KR/25G-KR and 32GFC/16GFC/8GFC/4GFC. To operate across a wide range of data-rates, from 0.3 to 28.05Gb/s, with low jitter, we develop a PLL architecture with two LC-VCOs and one ring VCO with a data-rate-adjustment technique by controlling an LDO. Our test chip is fabricated in 28nm CMOS. Our signal conditioner is the demonstration to achieve the BER <10 -12 PRBS31 at 100G-KR4 in a 40dB chip-to-chip backplane with two connectors by using the 36-tap DFE to cancel the reflection and to operate across a wide range of data-rates from 0.3 to 28.05Gb/s.

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection

“…The proliferation of copper-based links in this area can be mainly attributed to the advancements of CMOS technologies and circuit techniques. By utilizing advanced CMOS technologies and equalization techniques, operations at higher than 25 Gb/s even in severe loss conditions of more than 40 dB were achieved [ 9 , 10 , 11 ]. Recently, circuit designers attempt to overcome the limitations of copper by introducing a pulse-amplitude-modulation (PAM) signaling that can enhance the effective data rate for the same loss condition as the conventional binary signaling [ 12 , 13 , 14 , 15 ].…”

A wideband low-jitter PLL with an optimized Ring-VCO

“…Hence, the Ring-VCO based PLL is preferable in applications due to its small area, wide range of tuning property, high insensitivity to magnetic coupling, and easy integration. The poor jitter performance of the Ring-VCO based PLL, however, brings difficulties in providing high quality clocks [6,7,8,9].…”

Double-Rate Tomlinson-Harashima Precoding for Multi-Valued Data Transmission

“…1, the low-pass effect of interconnections introduces ISI, which causes bit errors due to the difficulty of 0 or 1 detection at the receiver. Such ISI can be countered by applying inverse channel responses using signal processing (e.g., preemphasis, continuous time linear equalizers (CTLEs) and decision feedback equalizers (DFEs)) [1], [2].…”