3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS

Cui, Delong; Zhang, Heng; Huang, Nick; Nazemi, Ali; Catli, Burak; Rhew, Hyo Gyuem; Zhang, Bo; Momtaz, Afshin; Cao, Jun

doi:10.1109/isscc.2016.7417905

Cited by 59 publications

(7 citation statements)

References 5 publications

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“…To increase the sampling speed without degrading the 𝐹𝑂𝑀 𝐴𝐷𝐶 , time interleaving ADCs are used which run at lower sampling speed. However, these require power-hungry front-end drivers and are prone to timing and gain mismatches [31], [32]. Hence they have limited ENOB and require high power e.g.…”

Section: A Ultra-high-speed Adcmentioning

confidence: 99%

Low Power Analog Processing for Ultra-High-Speed Receivers With RF Correlation

Lota

Demosthenous

2023

IEEE Access

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Ultra-high-speed data communication receivers (Rxs) conventionally require analog digital converters (ADC)s with high sampling rates which have design challenges in terms of adequate resolution and power. This leads to ultra-high-speed Rxs utilising expensive and bulky high-speed oscilloscopes which are extremely inefficient for demodulation, in terms of power and size. Designing energy-efficient mixedsignal and baseband units for ultra-high-speed Rxs requires a paradigm approach detailed in this paper that circumvents the use of power-hungry ADCs by employing low-power analog processing. The low-power analog Rx employs direct-demodulation with RF correlation using low-power comparators. The Rx is able to support multiple modulations with highest modulation of 16-QAM reported so far for direct-demodulation with RF correlation. Simulations using Matlab, Simulink R2020a® indicate sufficient symbol-error rate (SER) performance at a symbol rate of 8 GS/s for the 71 GHz Urban Micro Cell and 140 GHz indoor channels. Power analysis undertaken with current analog, hybrid and digital beamforming approaches requiring ADCs indicates considerable power savings. This novel approach can be adopted for ultra-high-speed Rxs envisaged for beyond fifth generation (B5G)/sixth generation (6G)/ terahertz (THz) communication without the powerhungry ADCs, leading to low-power integrated design solutions.

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Section: A Ultra-high-speed Adcmentioning

confidence: 99%

Low Power Analog Processing for Ultra-High-Speed Receivers With RF Correlation

Lota

Demosthenous

2023

IEEE Access

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“…A VGA is often designed for swing adjustment of the DFE input. The most popular VGA circuit is based on a degenerated differential pair, which consists of a programmable resistor [15], [16]. This kind of VGA has the advantages of good linearity and low input capacitance due to its simple structure.…”

Section: B Vga and Buffermentioning

confidence: 99%

A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOS

Wang

et al. 2022

IEEE Trans. Circuits Syst. I

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This paper presents a four-level pulse amplitude modulation (PAM-4) receiver that incorporates a continuous time linear equalizer, a variable gain amplifier, a phase interpolatorbased clock and data recovery, and a 4-tap direct decision feedback equalizer (DFE) for moderate channel loss applications in wireline communication. A dynamic current-mode logic comparator (DCMLC) is proposed and employed in the DFE. The DCMLC, which adopts dynamic logic, breaks the trade-off between the bandwidth and the clock to Q delay in the traditional current-mode logic comparator (CMLC). Compared with the traditional CMLC, the DCMLC reduces the clock to Q delay by 36%, which allows the implementation of a 4-tap direct DFE. Moreover, the first tap feedback signals are directly tapped from the output of the DCMLC, allowing the first tap feedback current to initiate 0.5UI before the decision clock. The PAM-4 receiver prototype is fabricated in a 65nm CMOS process. At a data rate of 56-Gbps, it can compensate for up to 20.17dB loss and achieve a bit error rate < 1E-10 with a power efficiency of 4.75 pJ/bit. Index Terms-Receiver (RX), four-level pulse amplitude modulation (PAM-4), decision feedback equalizer (DFE), clock and data recovery (CDR). I. INTRODUCTIONT HE ever-increasing bandwidth requirements of communication systems have driven wireline transceivers to operate at speed of up to 56-Gbps, which has promoted the recent development of high-speed I/O standards using fourlevel pulse modulation (PAM-4) [1], [2]. In PAM-4 signaling, four levels are used to represent 2-bit information (LSB and MSB), which doubles the bandwidth utilization compared with the non-return-to-zero (NRZ) signaling. The increase of Manuscript

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“…It refers to a 1:2 or 2:1 Wilkinson splitting or combining unit. c. We use 0.89mm 2 [60] and 0.32mm 2 [83] for SerDes receiver and transmitter respectively. They are fabricated in 28nm and 16nm CMOS.…”

Section: E Summary Of Specifications Of Circuits Blocks For Transmitmentioning

confidence: 99%

“…P SerDes scales with the number of independent data stream U due to the distributed digital precoding. The figure-of-merit of SerDes is adopted as FOM SerDes = 10mW/(Gb/s) [60] in this work. Note here we use BW OS as the oversampled data rate after considering a factor of 2 oversampling ratio, i.e., BW OS = 1.7GS/s.…”

Section: A Digital Signal Processing Powermentioning

confidence: 99%

Performance, Power, and Area Design Trade-Offs in Millimeter-Wave Transmitter Beamforming Architectures

Han

Ramesh

Gallagher

et al. 2019

IEEE Circuits Syst. Mag.

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Millimeter wave (mmW) communications is viewed as the key enabler of 5G cellular networks due to vast spectrum availability that could boost peak rate and capacity. Due to increased propagation loss in mmW band, transceivers with massive antenna array are required to meet link budget, but their power consumption and cost become limiting factors for commercial systems. Radio designs based on hybrid digital and analog array architectures and the usage of radio frequency (RF) signal processing via phase shifters have emerged as potential solutions to improve radio energy efficiency and deliver performances close to conventional digital antenna arrays. In this paper, we provide an overview of the state-of-the-art mmW massive antenna array designs and comparison among three array architectures, namely digital array, partially-connected hybrid array (sub-array), and fully-connected hybrid array. The comparison of performance, power, and area for these three architectures is performed for three representative 5G downlink use cases, which cover a range of pre-beamforming signal-to-noise-ratios (SNR) and multiplexing regimes. This is the first study to comprehensively model and quantitatively analyze all design aspects and criteria including: 1) optimal linear precoder, 2) impact of quantization error in digital-to-analog converter (DAC) and phase shifters, 3) RF signal distribution network, 4) power and area estimation based on state-of-theart mmW circuits including baseband digital precoding, digital signal distribution network, high-speed DACs, oscillators and mixers, phase shifters, RF signal distribution network, and power amplifiers. Our simulation results show that the fully-digital array is the most power and area efficient compared against optimal design for each architecture. Our analysis shows digital array benefits greatly from multi-user multiplexing. The analysis also reveals that sub-array is limited by reduced beamforming gain due to array partitioning, and system bottleneck of the fullyconnected hybrid architecture is the excessively complicated and power hungry RF signal distribution network.

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3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS

Cited by 59 publications

References 5 publications

Low Power Analog Processing for Ultra-High-Speed Receivers With RF Correlation

Low Power Analog Processing for Ultra-High-Speed Receivers With RF Correlation

A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOS

Performance, Power, and Area Design Trade-Offs in Millimeter-Wave Transmitter Beamforming Architectures

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