2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits

Krämer, Andreas; Denker, John S.; Flower, B.; Moroney, J.

doi:10.1145/224081.224115

Cited by 163 publications

(68 citation statements)

References 10 publications

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“…The Two Phase Adiabatic Static Clocked Logic (2-PASCL) uses two phase clocking split level sinusoidal power supply's it has both symmetrical and unsymmetrical power clocks where one clock is in phase while the other is out of phase [8]. The circuit has two diodes in its construction where one diode is placed between the output node and power clock, and another diode connected between one of the terminals of NMOS and power source.…”

Section: 2-phase Adiabatic Stratic Clock Cmos Logic (2-pascl)mentioning

confidence: 99%

Energy Efficient Design of Logic Circuits Using Adiabatic Process

Chitra¹,

Hemavathi²,

Ganesan³

2017

IJET

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Abstract-In today's electronic industry the Low power has emerged a principle theme. The most important features of modern electronic equipment is energy efficiency, it is designed using high speed and its portable applications. Power consuming can be reduced by adopting different style which is said to be excellent solution to low powerelectronic appliances. The adiabatic logic will be used as an efficient energytechnique for digital designs in this paper. The proposed system offers low power dissipation when compared to conventional CMOSlogic [1-6]. This paper provides full adder in various adiabatic logic styles and its results are compared to conventional CMOS logic. This simulation output specifiesas that proposed system is beneficial for various low power digital applications. Keywords-Adiabatic logic, Charge improvement, Low power, Energy efficient digital designs, Sinusoidal power clock.I. Introduction Power consumption plays amajor role in the today's VLSI technologies. In today's world many of the electronic appliances are portable, they require more battery storage which can be solved only using low power circuits that are internally structured. Thus the efficiency of energy has become importantdistress in the portable devices to get good results with less power dissipation. Once the power dissipation in a equipment is increased means additional design is important to cool the equipment and safeguard the equipment from thermal breakdown. This output leads to increase in total area of component. In order to solve these problems the power consumption of the design is to be decreased by including various low power styles. The circuit will be more efficient if the power dissipation is lower. In some of the previous decades CMOS tool plays a vital role in creating less power overwhelming equipments. CMOS plays a superior role while comparing with various logic families and previous low power designs. During to the switching of the devices from one to another state and due to the charging and discharging of load capacitor in the output terminal the power consumption is taking place in conventional CMOS design. By reducing the voltage supply, terminal capacitance value and switching of devices the power dissipation in conventional CMOS technology can be decreased. But by replacing the values of such parameters will corrupt the performance of device. Therefore for an efficient low power consumption compare to CMOS technique adiabatic technique will be provide better results. This proposed model is based on energy recovery principle with energy efficient technique known as adiabatic logic.In this paper instead of discharging, the regained energy is returned back to power supply that decreases the whole power consumption. Here the results of full adder is calculated using various adiabatic logic and its output is compared with conventional CMOS design. As full adder is one of the basic building block of adder designs, this paper is concerned on its design. The performance was evaluated in various adiabatic styl...

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Section: 2-phase Adiabatic Stratic Clock Cmos Logic (2-pascl)mentioning

confidence: 99%

Energy Efficient Design of Logic Circuits Using Adiabatic Process

Chitra¹,

Hemavathi²,

Ganesan³

2017

IJET

View full text Add to dashboard Cite

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“…The needed signal waveforms are equivalent to the signals for Efficient Charge Recovery Logic (ECRL) and 2N-2N2P (Moon et al, 1996;Kramer et al, 1995). These families use symmetrical trapezoidal supply voltages and dual rail encoded input/output signals.…”

Section: Introductionmentioning

confidence: 99%

Adiabatic circuits: converter for static CMOS signals

et al. 2003

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Abstract. Ultra low power applications can take great advantages from adiabatic circuitry. In this technique a multiphase system is used which consists ideally of trapezoidal voltage signals. The input signals to be processed will often come from a function block realized in static CMOS. The static rectangular signals must be converted for the oscillating multiphase system of the adiabatic circuitry. This work shows how to convert the input signals to the proposed pulse form which is synchronized to the appropriate supply voltage.By means of adder structures designed for a 0.13 µm technology in a 4-phase system there will be demonstrated, which additional circuits are necessary for the conversion. It must be taken into account whether the data arrive in parallel or serial form. Parallel data are all in one phase and therefore it is advantageous to use an adder structure with a proper input stage, e.g. a Carry Lookahead Adder (CLA). With a serial input stage it is possible to read and to process four signals during one cycle due to the adiabatic 4-phase system. Therefore input signals with a frequency four times higher than the adiabatic clock frequency can be used. This reduces the disadvantage of the slow clock period typical for adiabatic circuits. By means of an 8 bit Ripple Carry Adder (8 bit RCA) the serial reading will be introduced. If the word width is larger than 4 bits the word can be divided in 4 bit words which are processed in parallel. This is the most efficient way to minimize the number of input lines and pads. At the same time a high throughput is achieved.

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“…In this paper, a high efficiency power supply generator is presented, which can be used for logic circuits implemented using three adiabatic families, namely ECRL Jeong, 1996, 1998), PFAL (Vetuli et al, 1996;Blotti et al, 2000), and 2N-2N2P (Kramer et al, 1995;Liu and Lau, 1998). These families require, as power supplies, four trapezoidal waveforms equally spaced in phase.…”

Section: Introductionmentioning

confidence: 99%

Resonant 90 degree shifter generator for 4-phase trapezoidal adiabatic logic

et al. 2003

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Abstract. Many adiabatic logic families make use of multi phase trapezoidal or sinusoidal power clocks to recover the energy stored in the load capacitances. A key aspect for the evaluation of the performance of adiabatic logic is then the study of a system that includes the power clock generator. A four-phase trapezoidal power clock generator, according to the requirements of the most promising architectures, namely the ECRL and PFAL, has been designed and simulated. The proposed circuit, realized with a double-well 0.25 µm CMOS technology and external inductors, is a resonant generator designed to oscillate at a frequency of 7 MHz, which is within the optimum frequency range for adiabatic circuits realized with this CMOS technology. The generator has been simulated with the equivalent load of fifty 1-bit adders and the operating behavior of a 4-bit adder has been evaluated. The key aspects of a generator for adiabatic logic are its power consumption and the phase relationships between its output signals. The proposed generator has a conversion efficiency higher than 80%, and it is robust with respect to variations of technology parameters. The four power supplies exhibit the correct relationship of phase also in the presence of no equally distributed loads.

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2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits

Cited by 163 publications

References 10 publications

Energy Efficient Design of Logic Circuits Using Adiabatic Process

Energy Efficient Design of Logic Circuits Using Adiabatic Process

Adiabatic circuits: converter for static CMOS signals

Resonant 90 degree shifter generator for 4-phase trapezoidal adiabatic logic

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