Energy Efficient Design of Logic Circuits Using Adiabatic Process

Abstract

Abstract-In today's electronic industry the Low power has emerged a principle theme. The most important features of modern electronic equipment is energy efficiency, it is designed using high speed and its portable applications. Power consuming can be reduced by adopting different style which is said to be excellent solution to low powerelectronic appliances. The adiabatic logic will be used as an efficient energytechnique for digital designs in this paper. The proposed system offers low power dissipation when compared to conventional CMOSlogic [1-6]. This paper provides full adder in various adiabatic logic styles and its results are compared to conventional CMOS logic. This simulation output specifiesas that proposed system is beneficial for various low power digital applications. Keywords-Adiabatic logic, Charge improvement, Low power, Energy efficient digital designs, Sinusoidal power clock.I. Introduction Power consumption plays amajor role in the today's VLSI technologies. In today's world many of the electronic appliances are portable, they require more battery storage which can be solved only using low power circuits that are internally structured. Thus the efficiency of energy has become importantdistress in the portable devices to get good results with less power dissipation. Once the power dissipation in a equipment is increased means additional design is important to cool the equipment and safeguard the equipment from thermal breakdown. This output leads to increase in total area of component. In order to solve these problems the power consumption of the design is to be decreased by including various low power styles. The circuit will be more efficient if the power dissipation is lower. In some of the previous decades CMOS tool plays a vital role in creating less power overwhelming equipments. CMOS plays a superior role while comparing with various logic families and previous low power designs. During to the switching of the devices from one to another state and due to the charging and discharging of load capacitor in the output terminal the power consumption is taking place in conventional CMOS design. By reducing the voltage supply, terminal capacitance value and switching of devices the power dissipation in conventional CMOS technology can be decreased. But by replacing the values of such parameters will corrupt the performance of device. Therefore for an efficient low power consumption compare to CMOS technique adiabatic technique will be provide better results. This proposed model is based on energy recovery principle with energy efficient technique known as adiabatic logic.In this paper instead of discharging, the regained energy is returned back to power supply that decreases the whole power consumption. Here the results of full adder is calculated using various adiabatic logic and its output is compared with conventional CMOS design. As full adder is one of the basic building block of adder designs, this paper is concerned on its design. The performance was evaluated in various adiabatic styl...