Adiabatic circuits: converter for static CMOS signals

Abstract

Abstract. Ultra low power applications can take great advantages from adiabatic circuitry. In this technique a multiphase system is used which consists ideally of trapezoidal voltage signals. The input signals to be processed will often come from a function block realized in static CMOS. The static rectangular signals must be converted for the oscillating multiphase system of the adiabatic circuitry. This work shows how to convert the input signals to the proposed pulse form which is synchronized to the appropriate supply voltage.By means of adder structures designed for a 0.13 µm technology in a 4-phase system there will be demonstrated, which additional circuits are necessary for the conversion. It must be taken into account whether the data arrive in parallel or serial form. Parallel data are all in one phase and therefore it is advantageous to use an adder structure with a proper input stage, e.g. a Carry Lookahead Adder (CLA). With a serial input stage it is possible to read and to process four signals during one cycle due to the adiabatic 4-phase system. Therefore input signals with a frequency four times higher than the adiabatic clock frequency can be used. This reduces the disadvantage of the slow clock period typical for adiabatic circuits. By means of an 8 bit Ripple Carry Adder (8 bit RCA) the serial reading will be introduced. If the word width is larger than 4 bits the word can be divided in 4 bit words which are processed in parallel. This is the most efficient way to minimize the number of input lines and pads. At the same time a high throughput is achieved.

Low-power interface circuits between adiabatic and standard CMOS circuits

“…The CMOS-adiabatic interfaces use the proposed interface based on PCFF (Fig. 11) and the circuit reported in [10,11] (Fig. 9), respectively.…”

“…Several interface circuits have been proposed [8][9][10][11]. In [8], the adiabatic-CMOS interface is realized by sampling the peak voltage of adiabatic signals using a C 2 MOS flipflop.…”

“…The literatures [10] and [11] proposed a design scheme for the CMOS-adiabatic interfaces using a adiabatic signal converter and a rectangle-wave clock generator that controls a flip-flop to synchronize CMOS signals with the adiabatic ones. Although these works realize the demanded functions of the interface circuits, they are suffered from considerable large energy dissipations [8][9][10][11]. Recently, several new low-power adiabatic-CMOS and CMOS-adiabatic interfaces have been presented and verified using SPICE simulations in [12].…”

An Adiabatic Architecture for Linear Signal Processing

“…The presented architecture is an array of locally connected CORDIC devices that resembles the familiar triangular array for computing a QR decomposition (Haykin, 1996). It is depicted in Fig.…”

“…The hyperbolic mode can also be used to carry out one step of the Schur Algorithm and can thus be used to efficiently compute the QR decomposition of a matrix with a Toeplitz-derived structure (Kailath and Chun, 1994). These matrices appear in time-invariant singleand multi-user systems (Vollmer et al, 1999(Vollmer et al, , 2001).…”