28.2 A 0.29mm&lt;sup&gt;2&lt;/sup&gt; frequency synthesizer in 40nm CMOS with 0.19ps&lt;inf&gt;rms&lt;/inf&gt; jitter and &amp;#x003C;-100dBc reference spur for 802.11ac

Hsueh, Yu-Li; Cho, Lan-Chou; Shen, Chih-Hsien; Tsai, Yi‐Fang; Chueh, Tzu-Chan; Chang, Tsin‐Yuan; Hsu, Jui-Lin; Zhan, Jing-Hong Conan

doi:10.1109/isscc.2014.6757518

Cited by 15 publications

(9 citation statements)

References 7 publications

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“…The reference doubler technique is adopted to double the 26-52 MHz. The duty cycle issue is calibrated by using the method in [21]. A time amplifier (TA) [22] is used to improve the coarse TDC resolution from 20-2.5 ps.…”

Section: B Wide Loop-bandwidth Fractional-n Dpllmentioning

confidence: 99%

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

Liu

Sun

Tang

et al. 2018

IEEE J. Solid-State Circuits

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This paper presents a Bluetooth low-energy (BLE) transceiver (TRX) achieving ultra-low-power operation for Internet-of-Things (IoT) applications. The proposed TRX utilizes a wide-bandwidth low-power fractional-N digital phase-locked loop (DPLL) as a central component to perform multiple roles: a direct frequency modulator for the transmitter (TX), an analogto-digital converter (ADC) for the receiver (RX), a local oscillator for RX, and a frequency and phase synchronizer for the RX. The DPLL-based single-path downconversion method is adapted to halve the analog baseband circuit to further reduce the power consumption while maintaining a high interference rejection. A DPLL-based ADC with a digital-to-analog converter feedback greatly improves the ADC dynamic range, which improves the RX sensitivity and interference tolerance. By maximally reducing the required radio frequency and analog front-end components in RX, an RX power consumption of 2.3 mW is achieved with a −94 dBm sensitivity. The RX also satisfied all interference requirements with a certain margin. A 5.0-mW TX is achieved when delivering an output power of 0 dBm with a frequency-shift keying error of only 1.89%.

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Section: B Wide Loop-bandwidth Fractional-n Dpllmentioning

confidence: 99%

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

Liu

Sun

Tang

et al. 2018

IEEE J. Solid-State Circuits

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“…To improve the in-band phase noise, a 4b 2-ps-resolution TA-TDC [7] and a reference doubler are implemented. The duty cycle issue of the doubler [15] is calibrated by using the method proposed in [16]. The proposed 10b isolated constant-slope DTC enhances the FOM of the fractional-N ADPLL, thanks to the good linearity and power efficiency.…”

Section: Sub-mw Fractional-n Adpll Architecturementioning

confidence: 99%

A Sub-mW Fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math> </inline-formula> ADPLL With FOM of −246 dB for IoT Applications

Liu

Tang

Sun

et al. 2018

IEEE J. Solid-State Circuits

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This paper presents a sub-mW fractional-N all-digital phase-locked loop (ADPLL) with scalable power consumption, which achieves an figure of merit (FOM) of −246 dB. The proposed 10-b ultralow-power isolated constant-slope digitalto-time converter (DTC) achieves a 580-fs resolution and a measured integral nonlinearity (INL) of 870 fs with 0.14-mW power consumption at 52 MS/s. A narrow-range time amplifier (TA)-time-to-digital converter (TDC) with gain calibration minimizes both the in-band phase noise degradation and the loop-bandwidth variation. In addition, a coarse-DPLL is introduced with dead-zone function, which reduces the phase lock time to 4.2 µs at a 13-MHz frequency error. The coarse-DPLL monitors large frequency and phase jump in the background while consuming almost zero power. In an ultralow power mode, the proposed fractional-N ADPLL consumes a 0.65-mW power with a 26-MHz reference. A rms jitter of 1.00 ps and −50-dBc in-band fractional spur are achieved with a −242-dB FOM. In high-performance mode, a reference doubler is utilized, the jitter and spurs can be improved to 535 fs and −56 dBc, respectively, while consuming 0.98 mW. The proposed ADPLL with scalable power and jitter performance can be utilized for Internet-of-Things (IoT) applications, such as Bluetooth low energy (BLE) and Wi-Fi networks.

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“…N EGATIVE voltage supply has been traditionally employed to implement low-voltage source-side erase operation in flash-EEPROM memories [1], [2], and biasing of III-V depletion mode devices for circuits such as Gallium Nitride (GaN) based RF power amplifier [3]- [5]. In recent times, the potential of negative voltage input has been explored for several upcoming applications, such as biphasic tissue stimulation [6], [7], static-leakage reduction [8] and high-performance oscillators [9], [10]. In Fig.…”

Section: Introductionmentioning

confidence: 99%

A Low-Noise, Positive-Input, Negative-Output Voltage Generator for Low-to-Moderate Driving Capacity Applications

Khanna

Boon

Choi

et al. 2019

IEEE Trans. Circuits Syst. I

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28.2 A 0.29mm<sup>2</sup> frequency synthesizer in 40nm CMOS with 0.19ps<inf>rms</inf> jitter and <-100dBc reference spur for 802.11ac

Cited by 15 publications

References 7 publications

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

A Sub-mW Fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math> </inline-formula> ADPLL With FOM of −246 dB for IoT Applications

A Low-Noise, Positive-Input, Negative-Output Voltage Generator for Low-to-Moderate Driving Capacity Applications

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