27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS

Wu, Jiangfeng; Chou, Acer; Li, Tianwei; Wu, Rong; Wang, Tao; Cusmai, G.; Lin, Sha-Ting; Yang, Cheng-Hsun; Unruh, Gregory; Dommaraju, Sunny Raj; Zhang, Mo M.; Yang, Po Tang; Lin, Wei‐Ting; Chen, Xi; Koh, Dongsoo; Dou, Qingqi; Geddada, Hemasundar Mohan; Hung, Juo-Jung; Brandolini, M.; Shin, Young Jae; Huang, Hung-Sen; Chen, Chunying; Venes, Ardie

doi:10.1109/isscc.2016.7418109

Cited by 26 publications

(6 citation statements)

References 5 publications

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“…This puts forward high requirements for device speed, circuit structure and system debugging, thus increasing the difficulty of system implementation [4,5]. Although the sampling rate of ultra-high speed analog-todigital converter (ADC) existing in the prior art can reach several or tens of GHz [6][7][8][9], the ADC chip still cannot meet the requirements of high resolution and high sampling rate for precision measurement at the same time because of the limitations of the integrated process. In order to improve the ability of the acquisition system to capture signals with the existing ADC technology, many scholars began to search the alternative sampling methods including time-interleaved sampling (TIS) theory [10] and multi-coset sampling (MCS) [11,12], which can both multiply the sampling rate but have high implementation Electronics 2022, 11, 2098 2 of 14 complexity.…”

Section: Introductionmentioning

confidence: 99%

Precision Measurement System of High-Frequency Signal Based on Equivalent-Time Sampling

Zang¹,

Zhao²,

Lu³

et al. 2022

Electronics

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A high frequency periodic signal measurement system based on equivalent sampling method is developed. A high-speed sampling voltage tracking circuit, the core component of the system, is described in detail. The circuit can transform the amplitude corresponding to different phase points of the signal undertest into the equivalent DC level through successive approximation of multiple periods. The measurement system designed in this paper completes digital sampling with high accuracy only by connecting the low-cost voltage tracking circuit to the existing commercial instruments, such as two-channel waveform generator and high-precision digital multimeter, which makes the method easy to be generalized. The special structure of the sampling tracking circuit greatly reduces the influence of random noise and time jitter on the measurement results. The experimental results show that the non-linearity error of the system is as low as 0.002%, the bandwidth can reach 200 MHz, and the uncertainty of measuring the RMS of AC voltage with peak value of ±1 V and frequency of 10 kHz, 100 kHz and 1 MHz can reach 2.8 × 10−4 V, 4.6 × 10−4 V and 2.0 × 10−4 V (k = 2), respectively.

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Section: Introductionmentioning

confidence: 99%

Precision Measurement System of High-Frequency Signal Based on Equivalent-Time Sampling

Zang¹,

Zhao²,

Lu³

et al. 2022

Electronics

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“…To ensure a sufficiently high input BW, all these designs employ a static front-end buffer. This buffer often dissipates more power than the ADC itself, significantly deteriorates the linearity and noise performance, and severely limits the available swing, unless over-voltage or multiple supplies are used [1][2][3][4][5].…”

mentioning

confidence: 99%

“…This work aims to boost the input BW and dynamic performance, while minimizing the power of GHz-range high-resolution ADCs, with a 5GS/s passive-sampling, fully dynamic, TI 3-stage pipelined-SAR hybrid. Removing the front-end buffer offers at least 2× power reduction compared to [1][2][3][4][5], while an input BW larger than 6GHz and a Nyquist performance of 9.4ENOB and 160.5dB FoM S are enabled by the combination of: (1) very low resistance/capacitance passive input network and proper on-chip termination; (2) on-chip clock division and distribution with negligible jitter; (3) optimized hybrid sub-ADC design to deliver maximum speed × resolution/power; and (4) on-chip co-designed sub-ADC/TI analog-digital calibration to enhance performance. Figure 3.3.1 illustrates the ADC architecture.…”

mentioning

confidence: 99%

3.3 A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoM<inf>S</inf> in 28nm CMOS

Ramkaj

Ramos

Lyu

et al. 2019

2019 IEEE International Solid- State Circuits Conference - (ISSCC)

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Emerging 5G communication systems require ADCs to directly digitize wide bandwidth (BW) signals with high spectral purity at low power consumption. Current state-of-the-art solutions include mainly time-interleaved (TI) pipelined [1-4] or pipelined-SAR [5] architectures, enhanced by digital calibration. To ensure a sufficiently high input BW, all these designs employ a static front-end buffer. This buffer often dissipates more power than the ADC itself, significantly deteriorates the linearity and noise performance, and severely limits the available swing, unless over-voltage or multiple supplies are used [1][2][3][4][5].

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“…Consequently, amplifiers and comparators suffer from diminishing returns in their on fine technology nodes (e.g., 28nm, 16nm, etc.) likewise degrades quickly when the conversion rate increases to multi-GS/s [8][9][10]. In the perspective of circuit and architecture, several critical issues undesirably limit the design and realization of stateof-the-art high-speed and high-resolution ADCs.…”

Section: List Of Tablesmentioning

confidence: 99%

“…In view of the substantially increased difficulty to minimize ∆trms < 50fs [9,44], it is not unexpected that State-of-the-Art high-speed ADCs that target GHz or multi-GHz input bandwidth [9,11,22] are often designed with resolution ≤ 14 bits.…”

Section: Aperture Time and Jittermentioning

confidence: 99%

Design and monolithic realization of high-speed high-resolution analog-to-digital converters

Liu¹

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This PhD program pertains to the design and monolithic realization of high-speed high-resolution Analog-to-Digital Converters (ADCs), particularly pipeline-based and Successive Approximation Register (SAR)-based architectures, for next-generation telecommunication systems. The primary objectives are to increase the speed and the resolution of these ADCs by means of innovative techniques/approaches, yet with minimal hardware and power overheads, and accommodating the ever-finer technology nodes. Interestingly, although the design art of pipeline and SAR ADCs are well established, several aspects of state-of-the-art designs and realizations remain inadequate. These inadequacies include the Multiplying Digital-to-Analog Converter (MDAC) in pipeline-based ADCs constraining the resolution, and the conversion algorithm of SAR-based ADCs limiting the speed. For the pipeline-based ADC, we propose, design, and monolithically realize a novel time-interleaved (×2) 11bit 1GS/s SAR-assisted MDAC-free pipeline architecture. At the system level, we propose to employ a front-end sample-and-hold to mitigate the problematic timing mismatch between the two time-interleaved channel ADCs. We further propose to predetermine the MSB (Most Significant Bit) outside the channel ADCs to substantially simplify the requirement of the channel ADCs. At the block level, we propose an innovative MDAC-free pipeline architecture for the channel ADCs where the MDAC is absent-to the best of our knowledge, this is the first-ever reported MDAC-free pipeline ADC architecture. The significance of the MDAC-free feature is particularly valuable to the pipeline ADC design as the well-reported critical issues arising from the MDACs are largely circumvented. Particularly, this leads to higher speed and higher accuracy, yet with potentially reduced design complexity. Further, this

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27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS

Cited by 26 publications

References 5 publications

Precision Measurement System of High-Frequency Signal Based on Equivalent-Time Sampling

Precision Measurement System of High-Frequency Signal Based on Equivalent-Time Sampling

3.3 A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoM<inf>S</inf> in 28nm CMOS

Design and monolithic realization of high-speed high-resolution analog-to-digital converters

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