Design and monolithic realization of high-speed high-resolution analog-to-digital converters

Abstract

This PhD program pertains to the design and monolithic realization of high-speed high-resolution Analog-to-Digital Converters (ADCs), particularly pipeline-based and Successive Approximation Register (SAR)-based architectures, for next-generation telecommunication systems. The primary objectives are to increase the speed and the resolution of these ADCs by means of innovative techniques/approaches, yet with minimal hardware and power overheads, and accommodating the ever-finer technology nodes. Interestingly, although the design art of pipeline and SAR ADCs are well established, several aspects of state-of-the-art designs and realizations remain inadequate. These inadequacies include the Multiplying Digital-to-Analog Converter (MDAC) in pipeline-based ADCs constraining the resolution, and the conversion algorithm of SAR-based ADCs limiting the speed. For the pipeline-based ADC, we propose, design, and monolithically realize a novel time-interleaved (×2) 11bit 1GS/s SAR-assisted MDAC-free pipeline architecture. At the system level, we propose to employ a front-end sample-and-hold to mitigate the problematic timing mismatch between the two time-interleaved channel ADCs. We further propose to predetermine the MSB (Most Significant Bit) outside the channel ADCs to substantially simplify the requirement of the channel ADCs. At the block level, we propose an innovative MDAC-free pipeline architecture for the channel ADCs where the MDAC is absent-to the best of our knowledge, this is the first-ever reported MDAC-free pipeline ADC architecture. The significance of the MDAC-free feature is particularly valuable to the pipeline ADC design as the well-reported critical issues arising from the MDACs are largely circumvented. Particularly, this leads to higher speed and higher accuracy, yet with potentially reduced design complexity. Further, this