InAs/Si Hetero-Junction Nanotube Tunnel Transistors

Abstract

Hetero-structure tunnel junctions in non-planar gate-all-around nanowire (GAA NW) tunnel FETs (TFETs) have shown significant enhancement in ‘ON’ state tunnel current over their all-silicon counterpart. Here we show the unique concept of nanotube TFET in a hetero-structure configuration that is capable of much higher drive current as opposed to that of GAA NW TFETs.Through the use of inner/outer core-shell gates, a single III-V hetero-structured nanotube TFET leverages physically larger tunneling area while achieving higher driver current (ION) and saving real estates by eliminating arraying requirement. Numerical simulations has shown that a 10 nm thin nanotube TFET with a 100 nm core gate has a 5×normalized output current compared to a 10 nm diameter GAA NW TFET.

Phonon transmission at Si/Ge and polytypic Ge interfaces using full-band mismatch based models

“…In particular, interfaces between semiconducting materials of the column IV of the periodic table such as Si and Ge and/or III-V compounds open the way of performance enhancement in optoelectronics [8], thermoelectrics [9] and also electronics. For instance, tunnel Field Effect Transistors based on Si/Ge [10] or Si/InAs [11] interfaces are expected to improve the off-behavior of transistors.…”

Core-shell homojunction silicon vertical nanowire tunneling field-effect transistors

“…Some of the simulated data1012 show I on / I off ratios similar to the CS TFETs, but their low I on values even at high V DD would decrease operation speed along with significant power consumption. Compared to the CS TFETs, the TFETs with nanotube structure1214 also show the possibility to substitute the conventional MOSFETs through high I on and I on / I off ratio, but the process complexity and reliability such as two independent gate terminals for the core and shell regions and ultra-thin EOT of 0.5 nm still need to be solved. Overall, the CS TFETs show comparably high I on and I on / I off ratio under all V DD of 0.5, 0.7, 1.0 V and also show great potential to increase device density through vertical nanowire structure and to adopt the nanowire array easily due to the compatibility to present a three-terminal transistor platform.…”

“…Meanwhile, tunneling FETs (TFETs) have been considered as one of the promising alternatives to attain SS below 60 mV/dec and high on/off current ratio under low V DD for mobile applications23456789101112131415. TFETs obey tunneling transport at the source/channel junction by adopting different types of doping between the source and the drain as p-i-n structure.…”

“…Second, the tunneling area was increased through adaptation of a vertical nanowire structure to increase the device density and gate-to-channel controllability47 or modulation of the tunneling junction8. Additionally, equivalent oxide thickness (EOT) scaling or heterojunction using Ge or III-V materials was also shown to improve the DC performance by increasing gate-to-channel modulation or by decreasing tunneling barriers through low energy bandgap materials and tunneling masses, respectively131415. However, all these lateral TFETs perpendicular to the gate electric field pose challenges to obtain precise the source/channel junction aligned to the gate region for high I on 16.…”

Freeform electronics for advanced healthcare

“…To address this critical issue, we have designed a nanotube architecture based heterogeneous tunnel field effect transistor (TFET) with core-shell gate stacks (Fig. 2) [3,4]. Such device offers the highest performance (drive current) among all the reported TFETs with pinned subthreshold slope lesser than 60 mV/dec.…”