250 Mbyte/sec synchronous DRAM using a 3-stage-pipelined architecture

Takai,; Nagase,; Kitamura,; Koshikawa,; Yoshida, Minoru; Kobayashi, Kazuya; Obara,; Fukuzo,; Watanabe, Toru

doi:10.1109/vlsic.1993.920536

Cited by 12 publications

(7 citation statements)

References 2 publications

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“…Publisher Item Identifier S 0018-9200(97)06307-5. meet the needs of not only CPU but also cache and memory. The program execution time is given as (1) where , and are number of read references reaching a cache, number of stores in the program, cache miss rate, average number of cycles to complete a write operation, cycle time, and cache refill time, respectively [9]. Among them, or the total time required to replace the cache with new data from the SDRAM can be used to evaluate the performance of the SDRAM in the computer system without L2 cache.…”

Section: On-chip Cache Refill Timementioning

confidence: 99%

“…Fig. 1(a) shows the three-stage pipeline architecture of the column address path [1], [5]. The first stage is the address buffer stage.…”

Section: On-chip Cache Refill Timementioning

confidence: 99%

“…T HE synchronous DRAM (SDRAM) has been widely accepted as a DRAM which enhances speed without introducing revolutionary changes into the conventional DRAM architecture [1]- [8]. Owing to the synchronization of internal timing signals with the external clock which is shared with the CPU, it is easy to incorporate many high-speed functions into the SDRAM.…”

Section: Introductionmentioning

confidence: 99%

“…Different pipeline architectures have been widely employed in the SDRAM for high-speed operation [1], [3]- [8]. However, little discussion on their performances or comparison with each other has been reported.…”

Section: Introductionmentioning

confidence: 99%

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A study of pipeline architectures for high-speed synchronous DRAMs

Yoo

1997

IEEE J. Solid-State Circuits

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The performances of SDRAM's with different pipeline architectures are examined analytically on the basis of the time required to refill the on-chip cache of a Pentium CPU. The analysis shows that the cycle time of the conventional pipeline structures cannot be reduced because of its difficulty in distributing the access time evenly to each pipeline stage of the column address access path. On the contrary, the wave pipeline architecture can make the access path evenly divided and can increase the number of pipeline stages to achieve the shortest cache refill time. But the wave congestion at the output terminal of the wave pipeline path caused by access time fluctuation narrows the valid time window. The parallel registered wave pipeline architecture can remove the effect of access time fluctuation so that the cycle time is defined only by the data pulse width. If the data pulse width tw < 2 ns, even 500-MHz clock frequency can be obtained.

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Section: On-chip Cache Refill Timementioning

confidence: 99%

“…Fig. 1(a) shows the three-stage pipeline architecture of the column address path [1], [5]. The first stage is the address buffer stage.…”

Section: On-chip Cache Refill Timementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A study of pipeline architectures for high-speed synchronous DRAMs

Yoo

1997

IEEE J. Solid-State Circuits

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“…Beginning in the late 1990s as these new technologies developed, two DRAMs are of particular interest: direct Rambus DRAM [1] and DDR SDRAM [2]. The history of high-speed DRAM starts from the new technologies employed in these two DRAMs.…”

Section: Introductionmentioning

confidence: 99%