A study of pipeline architectures for high-speed synchronous DRAMs

Abstract

The performances of SDRAM's with different pipeline architectures are examined analytically on the basis of the time required to refill the on-chip cache of a Pentium CPU. The analysis shows that the cycle time of the conventional pipeline structures cannot be reduced because of its difficulty in distributing the access time evenly to each pipeline stage of the column address access path. On the contrary, the wave pipeline architecture can make the access path evenly divided and can increase the number of pipeline stages to achieve the shortest cache refill time. But the wave congestion at the output terminal of the wave pipeline path caused by access time fluctuation narrows the valid time window. The parallel registered wave pipeline architecture can remove the effect of access time fluctuation so that the cycle time is defined only by the data pulse width. If the data pulse width tw < 2 ns, even 500-MHz clock frequency can be obtained.

Tunnelling-based SRAM

“…SRAM has about four times faster random access times, and traditionally consumes the lowest standby power per bit (to below 1 pW/bit [73]). From recent developments, such as synchronous DRAM (SDRAM) using pipelined highspeed data transfer [83][84][85][86], standby power reduction through proper cell biasing techniques and optimized self-refresh timing [74], silicon-on-insulator (SOI) technology [87][88][89], novel dielectric materials [90], new high-speed interfaces [91][92][93]82], variable/dynamic-V T transistor circuits for sub-1-V operation [94][95][96][97], and the increasing value of memorycell density with the advent of the Ôsystem-on-a-chip' [98], it appears that DRAM will remain the memory backbone for future generations of silicon processors.…”

A 300 MHz burst-pipelined CMOS SRAM macro with folded bit-line scheme

“…[ 1,4] On the other approach, many cache SRAM's adopting variable pipeline schemes have been proposed. [3] As a result, recently, the access time has been improved to 1.811s -2.5ns. [2,5].…”