23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices

Kwon, Hye-Jung; Seo, Eunsung; Lee, Chan Yong; Seo, Young-Hun; Han, Gong-Heum; Kim, Hye‐Ran; Lee, Jong-Ho; Jang, M. S.; Do, Sung-Geun; Cho, Seung-Hyun; Park, Jae-Koo; Doo, Su-Yeon; Shin, Jangho; Jung, Sungjune; Kim, Hyoung-Ju; Im, Il; Cho, Beob-Rae; Lee, Jae-Woong; Lee, Jae-Youl; Yu, Ki-Hun; Kim, Hyung-Kyu; Jeon, Chul-Hee; Park, Hyunsoo; Kim, Sang-Sun; Lee, Seokho; Park, Jong‐Wook; Lee, Seung-Sub; Lim, Bo-Tak; Park, Jun-Young; Park, Yoon-Sik; Kwon, Hyuk‐Jun; Bae, Seung-Jun; Choi, Jung-Hwan; Park, Kwang-Il; Jang, Seong-Jin; Jin, Gyoyoung

doi:10.1109/isscc.2017.7870427

Cited by 19 publications

(20 citation statements)

References 1 publication

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“…The majority of the 8-byte data chunks are those that have only a single RowHammer bit flip (i.e., up to 6.9 million 8-byte data chunks with a single bit flip in one bank of module 𝐵13), which can be corrected using typical SECDED ECC [10,37,43,60,61,79,87,118]. However, our RowHammer access patterns can cause at least 3 (up to 7) bit flips in many single datawords, which the SECDED ECC cannot correct or detect, in all three vendor's modules.…”

Section: Bypassing System-level Ecc Using U-trrmentioning

confidence: 99%

“…The large number of RowHammer bit flips caused by our specialized access patterns has significant implications for systems protected by Error Correction Codes (ECC) [47,92,93,95]. Our analysis shows that the U-TRR-discovered access patterns can cause up to 7 bit flips at arbitrary locations in one 8-byte dataword, suggesting that typical ECC schemes capable of correcting one error/symbol and detecting two errors/symbols (e.g., SECDED ECC [10,37,43,60,61,79,87,118] and Chipkill [2,20,86]) cannot provide sufficient protection against RowHammer even in the presence of TRR mechanisms.…”

Section: Introductionmentioning

confidence: 99%

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Uncovering In-DRAM RowHammer Protection Mechanisms:A New Methodology, Custom RowHammer Patterns, and Implications

Hassan

Can

Kim

et al. 2021

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture

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The RowHammer vulnerability in DRAM is a critical threat to system security. To protect against RowHammer, vendors commit to security-through-obscurity: modern DRAM chips rely on undocumented, proprietary, on-die mitigations, commonly known as Target Row Refresh (TRR). At a high level, TRR detects and refreshes potential RowHammer-victim rows, but its exact implementations are not openly disclosed. Security guarantees of TRR mechanisms cannot be easily studied due to their proprietary nature.To assess the security guarantees of recent DRAM chips, we present Uncovering TRR (U-TRR), an experimental methodology to analyze in-DRAM TRR implementations. U-TRR is based on the new observation that data retention failures in DRAM enable a side channel that leaks information on how TRR refreshes potential victim rows. U-TRR allows us to (i) understand how logical DRAM rows are laid out physically in silicon; (ii) study undocumented on-die TRR mechanisms; and (iii) combine (i) and (ii) to evaluate the RowHammer security guarantees of modern DRAM chips. We show how U-TRR allows us to craft RowHammer access patterns that successfully circumvent the TRR mechanisms employed in 45 DRAM modules of the three major DRAM vendors. We find that the DRAM modules we analyze are vulnerable to RowHammer, having bit flips in up to 99.9% of all DRAM rows. CCS Concepts• Hardware → Dynamic memory; • Security and privacy → Hardware reverse engineering.

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Section: Bypassing System-level Ecc Using U-trrmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Uncovering In-DRAM RowHammer Protection Mechanisms:A New Methodology, Custom RowHammer Patterns, and Implications

Hassan

Can

Kim

et al. 2021

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture

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“…State-of-the-art ECC DDR DIMMs, for instance, consist of 8 DRAM devices and a further device for storing the ECC redundancy. Moreover, vendors recently introduced on-die ECC for LPDDR4 [24,26] to correct retention errors. With ECC the refresh rate can be lowered by 4×, which largely reduces the power consumption.…”

Section: Temperature Vs Reliabilitymentioning

confidence: 99%

The Dynamic Random Access Memory Challenge in Embedded Computing Systems

Jung

Weis

Wehn

2020

A Journey of Embedded and Cyber-Physical Systems

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Dynamic random access memories (DRAMs) are key components in all computing systems that require large working memory. Due to the strong increase in data volume in many embedded applications, such as machine learning, image processing, autonomous systems, etc., DRAMs largely impact the overall system performance and power consumption. In many of these applications, the overall system performance is often limited by the memory bandwidth or latency and not by the computation itself. Due to the dynamic storage scheme of DRAMs and shrinking technology nodes, reliability is also a major concern in current and future DRAMs. Therefore, new challenges arise, which we will discuss in this chapter. The most important metrics, which are typically considered for DRAM subsystems (especially in the high-performance computing (HPC) domain), are bandwidth, latency, and capacity. However, in the context of embedded systems it requires to consider further metrics, such as power, temperature, reliability, safety, and security. In the following we will highlight these challenges and refer to some of our recent contributions, which tackle these challenges.

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“…As the urgent demand for the miniaturization of microelectronics, people need search alternatives to current flash memory for next generation high-density universal memories. Resistance-switching memory with the metal-insulator-metal structure (MIM) could satisfy the demand due to the superior characteristics [1]. Huge numbers of physical analysis have been performed on the unknown mechanism of resistive switching.…”

Section: Introductionmentioning

confidence: 99%

“…However, the basic information about the composition of the conductive filament buried under the metal electrodes in both ECM and VCM has not been thoroughly understood. Kwon et al reported some regions blew off by the compressed excess oxygen gas in the Pt/TiO 2 /Pt stack after the forming process [1]. They felt that these regions might correspond to the locations where the conductive filaments have formed.…”

Section: Introductionmentioning

confidence: 99%

Conductive Path Formation by Aggregated Oxygen Ions in Titanium Dioxide: First-Principles Analyses

Li¹,

Li²,

Ji³

et al. 2015

Proceedings of the 2015 3rd International Conference on Machinery, Materials and Information Technology Applications

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A first-principle study on the conductive path formation induced by the aggregated O ions in the defected titanium dioxide (Ti 12 O 29) is reported. The result illustrates that the O interstitials induce the aggregation of the O-ions. Thus, the formation of the conductive path is attributed to the continuous O-O bonds among these aggregated O-ions. In the I-V and R-V curves with the transmission coefficients, we find the resistance difference of the Pt/Ti 12 O 29 /Pt device.

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23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices

Cited by 19 publications

References 1 publication

Uncovering In-DRAM RowHammer Protection Mechanisms:A New Methodology, Custom RowHammer Patterns, and Implications

Uncovering In-DRAM RowHammer Protection Mechanisms:A New Methodology, Custom RowHammer Patterns, and Implications

The Dynamic Random Access Memory Challenge in Embedded Computing Systems

Conductive Path Formation by Aggregated Oxygen Ions in Titanium Dioxide: First-Principles Analyses

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