21.6 A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS

Lee, Jongwoo; Han, Sang-Wook; Kang, Bongsoon; Bae, Jeong-Yeol; Jang, Jaehyuk; Oh, Sangyoon; Ahn, Seung‐Eon; Kang, Seong-Hoon; Bui, Quang-Diep; Son, Kyungjune; Lim, Hong Sik; Jeong, Daechul; Ni, Ronghua; Zuo, Yongrong; Jong, I.Y.; Yao, Chunhua; Heo, Sung; Cho, Thomas Byunghak; Kang, I-Seok

doi:10.1109/isscc.2019.8662353

Cited by 17 publications

(1 citation statement)

References 3 publications

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“…RF transceiver always is a functional interface between ADC and modems. It reduced the massive analog connectivity by delivering the same data rate using the same bandwidth (Lee et al , 2019). The data rate requirement is increasing as time passes and in advanced technologies such as new radio (NR) and 5G, the demand is very high.…”

Section: Theoretical Analysismentioning

confidence: 99%

Key techniques of ultra-low-power ADC and miniaturized RF transceiver circuits for 4G/LTE applications

Faheem

Azeem

Minhas

et al. 2022

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Purpose RF transceiver module is considered a vital part of any wireless communication system. This module consists of two important parts the RF transceiver and analog-to-digital converter (ADC). Usually, both these parts – RF transceiver and ADC – are used to enhance the perspective of size and power. The data processing in 4G communication makes hurdles and need research attention to make it faster and smaller in size. Accuracy and fast processing are the critical challenges in the modern communication system. Design/methodology/approach After theoretical and practical investigations, this research work proposes key new techniques for the RF transceiver module. These techniques will make RF transceiver small, power-efficient and on the other hand, make dual SAR-ADC more effective as well. The proposed design has no intermediate frequency where the RF transceiver is reduced its major blocks from five to four, which includes crystal oscillator, phase lock loop, power amplifier and low noise amplifier. Moreover, the shared circuitry is introduced in the architecture of the SAR-ADC for the production of dual outputs, specifically in bootstrapped switch and comparator. Findings The miniaturized RF transceiver and SAR-ADC are well tested separately before the plantation on the printed circuit board (PCB). The operating voltage and frequency of the RF transceiver module are 1.2 V and 5.8 GHz, where the sampling rate, bandwidth and output power are 25 MHz, 200 MHz and 5 dBm, respectively. The core area of the PCB is 58.13 mm2. The bandwidth efficiency is 93% using surface acoustic wave less transmitter. The circuit is based on the library of 90 nm CMOS technology. Originality/value The entire circuit is highly synchronized with the input and reference clocks to avoid self-interference.

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Section: Theoretical Analysismentioning

confidence: 99%

Key techniques of ultra-low-power ADC and miniaturized RF transceiver circuits for 4G/LTE applications

Faheem

Azeem

Minhas

et al. 2022

View full text Add to dashboard Cite

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A Jitter-Tolerant Referenceless Digital-CDR for Cellular Transceivers

Kim

Jin

et al. 2020

2020 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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A 0.55mm² 16.9mW Fully Integrated 0-to-200MHz System BW Wireless Direct Sampling Receiver in 14nm FinFET

Jang

Sung

Lee

et al. 2022

2022 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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21.6 A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS

Cited by 17 publications

References 3 publications

Key techniques of ultra-low-power ADC and miniaturized RF transceiver circuits for 4G/LTE applications

Key techniques of ultra-low-power ADC and miniaturized RF transceiver circuits for 4G/LTE applications

A Jitter-Tolerant Referenceless Digital-CDR for Cellular Transceivers

A 0.55mm² 16.9mW Fully Integrated 0-to-200MHz System BW Wireless Direct Sampling Receiver in 14nm FinFET

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21.6 A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS

Cited by 17 publications

References 3 publications

Key techniques of ultra-low-power ADC and miniaturized RF transceiver circuits for 4G/LTE applications

Key techniques of ultra-low-power ADC and miniaturized RF transceiver circuits for 4G/LTE applications

A Jitter-Tolerant Referenceless Digital-CDR for Cellular Transceivers

A 0.55mm2 16.9mW Fully Integrated 0-to-200MHz System BW Wireless Direct Sampling Receiver in 14nm FinFET

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Product

Resources

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A 0.55mm² 16.9mW Fully Integrated 0-to-200MHz System BW Wireless Direct Sampling Receiver in 14nm FinFET