A Jitter-Tolerant Referenceless Digital-CDR for Cellular Transceivers

Kim, Jaekwon; Ko, Young-Jun; Jin, Jahoon; Choi, Jaehyuk; Chun, Jung-Hoon

doi:10.1109/a-sscc48613.2020.9336143

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2022

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Cited by 3 publications

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“…The proposed CDR was fabricated in a 28 nm low-power CMOS technology with an area of 100 µm × 90 µm, as shown in Figure 13 [20]. The overall power consumption of the CDR, the CML-to-CMOS converter, and the bias generator was 13 mW from a 1-V supply at 10 Gb/s (12.7 mW for the CDR).…”

Section: Measurement Resultsmentioning

confidence: 99%

A Referenceless Digital CDR with a Half-Rate Jitter-Tolerant FD and a Multi-Bit Decimator

Kim

Jin

et al. 2022

Electronics

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A referenceless digital clock and data recovery (D-CDR) circuit using a half-rate jitter-tolerant frequency detector (FD) and a multi-bit decimator is presented. For a referenceless configuration, we introduced a half-rate jitter-tolerant digital quadricorrelator frequency detector (JT-DQFD). Additionally, we proposed a multi-bit decimator circuit that losslessly down-samples up/down data from a phase detector to reduce the recovered clock jitter. The down-sampled multi-bit phase information is processed by a digital loop filter to adjust the phase of the recovered clock. Fabricated in a 28-nm CMOS technology, the test chip achieves a power efficiency of 1.3 pJ/bit at 10 Gb/s.

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Section: Measurement Resultsmentioning

confidence: 99%