20nm DRAM: A new beginning of another revolution

Park, J. M.; Hwang, Young‐Ha; Kim, S.-W.; Han, Sangyong; Park, J. S.; Kim, Hyoju; Seo, Jung Woo T.; Kim, B. S.; Shin, Seungyong; Cho, C. H.; Nam, Seung; Hong, Hye Jin; Lee, K. P.; Jin, Gyoyoung; Jung, Eui S.

doi:10.1109/iedm.2015.7409774

Cited by 40 publications

(23 citation statements)

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“…This minimum device size is slightly smaller than that in [ 17 – 20 ], as shown in Table 3 . However, the minimum size of DGTFET DRAM is still larger than that of 20 nm/18 nm node 1T1C DRAM [ 31 ], which is the inherent shortcoming for DGTFET DRAM. But its advantages of capacitor-less, low power, and high RT cannot be ignored under the help of optimization of spacer engineering.…”

Section: Resultsmentioning

confidence: 99%

The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

Liu

Wang

et al. 2018

Nanoscale Res Lett

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The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, including the reduction of reading “0” current and extension of retention time. The simulation results show that spacers at the source and drain sides should apply the low-k and high-k dielectrics, respectively, which can enhance the reading “1” current and reduce reading “0” current. Applying this optimized spacer engineering, the DGTFET DRAM obtains the optimum performance-extremely low reading “0” current (10−14A/μm) and large retention time (10s), which decreases its static power consumption and dynamic refresh rate. And the low reading “0” current also enhances its current ratio (107) of reading “1” to reading “0”. Furthermore, the analysis about scalability reveals its inherent shortcoming, which offers the further investigation direction for DGTFET DRAM.

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Section: Resultsmentioning

confidence: 99%

The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

Liu

Wang

et al. 2018

Nanoscale Res Lett

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“…DRAM systems today have a process variation much less than this tolerable ±28% (56% cell to cell). For example, the capacitance dierence between two generation is only 10⇠15% [70]. Also, industry inventions on new DRAM capacitance structures signicantly increase the capacitance of DRAM cell and therefore reduce the impact of variation [70].…”

Section: Discussionmentioning

confidence: 99%

Drisa

Niu

Malladi

et al. 2017

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture

250

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Data movement between the processing units and the memory in traditional von Neumann architecture is creating the "memory wall" problem. To bridge the gap, two approaches, the memory-rich processor (more on-chip memory) and the compute-capable memory (processing-in-memory) have been studied. However, the rst one has strong computing capability but limited memory capacity/bandwidth, whereas the second one is the exact the opposite. To address the challenge, we propose DRISA, a DRAM-based Recongurable I n-Situ Accelerator architecture, to provide both powerful computing capability and large memory capacity/bandwidth. DRISA is primarily composed of DRAM memory arrays, in which every memory bitline can perform bitwise Boolean logic operations (such as NOR). DRISA can be recongured to compute various functions with the combination of the functionally complete Boolean logic operations and the proposed hierarchical internal data movement designs. We further optimize DRISA to achieve high performance by simultaneously activating multiple rows and subarrays to provide massive parallelism, unblocking the internal data movement bottlenecks, and optimizing activation latency and energy. We explore four design options and present a comprehensive case study to demonstrate signicant acceleration of convolutional neural networks. The experimental results show that DRISA can achieve 8.8⇥ speedup and 1.2⇥ better energy eciency compared with ASICs, and 7.7⇥ speedup and 15⇥ better energy eciency over GPUs with integer operations.

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“…First, fine-pitch metal line and contact resistance (R) increase drastically. The metal resistivity sharply increases below 20nm film thickness because of shrinking in metal volume and the surface scattering effect [51]. This increases the resistance of WLs and BLs.…”

Section: Key Design Challengesmentioning

confidence: 99%

“…Significant efforts have made on various aspects of DRAM designs including material (e.g., high-k metal gate to increase transistor speed), fabrication technology (e.g., filling air within spacers to reduce BL capacitance [51]), and cell structuring (e.g., deploying cells like honeycomb to increase cell spacing [51]) to increase DRAM density without sacrificing timing constraints. However, those incur substantial manufacturing costs, need time to be applied stably, or become one-time magic desiring a new solution (another magic) next time.…”

Section: Key Design Challengesmentioning

confidence: 99%

3D-Xpath

Lee

Sung

et al. 2018

Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques

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The advance of DRAM manufacturing technology slows down, whereas the density and performance needs of DRAM continue to increase. This desire has motivated the industry to explore emerging Non-Volatile Memory (e.g., 3D XPoint) and the high-density DRAM (e.g., Managed DRAM Solution). Since such memory technologies increase the density at the cost of longer latency, lower bandwidth, or both, it is essential to use them with fast memory (e.g., conventional DRAM) to which hot pages are transferred at runtime. Nonetheless, we observe that page transfers to fast memory often block memory channels from servicing memory requests from applications for a long period. This in turn significantly increases the high-percentile response time of latency-sensitive applications. In this paper, we propose a high-density managed DRAM architecture, dubbed 3D-XPath for applications demanding both low latency and high capacity for memory. 3D-XPath DRAM stacks conventional DRAM dies with high-density DRAM dies explored in this paper and connects these DRAM dies with 3D-XPath. Especially, 3D-XPath allows unused memory channels to service memory requests from applications when primary channels supposed to handle the memory requests are blocked by page transfers at given moments, considerably increasing the high-percentile response time. This can also improve the throughput of applications frequently copying memory blocks between kernel and user memory spaces. Our evaluation shows that 3D-XPath DRAM decreases high-percentile

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20nm DRAM: A new beginning of another revolution

Cited by 40 publications

References 1 publication

The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

Drisa

3D-Xpath

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