The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

Abstract

The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, including the reduction of reading “0” current and extension of retention time. The simulation results show that spacers at the source and drain sides should apply the low-k and high-k dielectrics, respectively, which can enhance the reading “1” current and reduce reading “0” current. Applying this optimized spacer engineering, the DGTFET DRAM obtains the optimum performance-extremely low reading “0” current (10−14A/μm) and large retention time (10s), which decreases its static power consumption and dynamic refresh rate. And the low reading “0” current also enhances its current ratio (107) of reading “1” to reading “0”. Furthermore, the analysis about scalability reveals its inherent shortcoming, which offers the further investigation direction for DGTFET DRAM.

A low power L-shaped gate bipolar impact ionization MOSFET based capacitorless one transistor dynamic random access memory cell

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The floating body effect of a WSe2 transistor with volatile memory performance

“…This unique design eliminates the redundant capacitor and could further scale down the size of DRAM arrays. 11–13 Nevertheless, it was predominantly performed based on bulk semiconductor materials including doped silicon 14,15 and III–V compounds. 16,17 Besides, the floating body effect will vanish if the body thickness is below 10 nm (a critical thickness for thin film materials) due to the super-coupling effect, eventually leading to the degraded properties of the 1T0C DRAM cell.…”

A Novel Dopingless Fin-Shaped SiGe Channel TFET with Improved Performance

“…But with the continuous progress of voltage scaling down, the unacceptable high-power consumption becomes a serious problem for modern ICs [1,2]. Benefit from the band-to-band tunneling mechanism, tunnel FET (TFET) with steep SS and low-power consumption bring a new solution to this problem and attracted lots of attention [3][4][5][6][7][8][9]. But the applications of conventional silicon-based TFETs are limited by the considerably low on-state current (I ON ), low switching ratio, severe ambipolar effect and large average subthreshold swing (SS) [1,7].…”

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