20-nm In<sub>0.8</sub>Ga<sub>0.2</sub>As MOSHEMT MMIC Technology on Silicon

Tessmann, A.; Leuther, A.; Heinz, Felix; Bernhardt, Frank; John, Laurenz; Maßler, H.; Czornomaz, Lukas; Merkle, Thomas

doi:10.1109/jssc.2019.2915161

Cited by 28 publications

(15 citation statements)

References 11 publications

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“…Minimum In0.52Al0.48As gate-insulator thickness is limited by gate leakage current; highk gate dielectrics truncate thermionic leakage current and reduce tunneling current at a given thickness while increasing the dielectric permittivity in the gated region providing a path forward. We report record f = 511 GHz for MOS-HEMT technology [1], [6]. While this technology has yet to surpass the maximum reported f of standard InP-based HEMTs [7], improvements in the access region design, optimization of channel design [8], and further scaling of the gate dielectric can further increase gm,e.…”

Section: Introductionmentioning

confidence: 89%

In₀.₅₃Ga₀.₄₇As/InAs Composite Channel MOS-HEMT Exhibiting 511 GHz f_τ and 256 GHz f _max

Markman

Brunelli

Goswami

et al. 2020

IEEE J. Electron Devices Soc.

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An In0.53Ga0.47As/InAs composite channel MOS-HEMT exhibiting peak f = 511 GHz and peak fmax = 285 GHz is demonstrated. Additionally, another device exhibiting peak f = 286 GHz and peak fmax = 460 GHz is reported. The devices have a 1 nm / 3 nm AlxOyNz interfacial layer and ZrO2 gate dielectric on a 2 nm / 4 nm In0.53Ga0.47As / InAs composite channel with a modulation doped In0.52Al0.48As back barrier. To reduce parasitic gate-source and gate-drain capacitances, a modulation doped In0.52Al0.48As / In0.53Ga0.47As / InAs composite quantum well is included between the gate edges and the N+ source and drain. Compared to [1], addition of an In0.52Al0.48As back-barrier, scaling of S/D metal spacing, and scaling of channel thickness has enabled improved transconductance and increased f. Short gate length devices fmax are limit by high RG due to poor metal filling of the T-Gate stem and large CDS due to a conductive etch stop layer. Long gate length devices exhibit better metal filling, reduced RG, and balanced fꚍ, fmax. Devices exhibit 10-15% DC-1 GHz gm,e suggesting that the high-k / semiconductor interface has low Dit.

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Section: Introductionmentioning

confidence: 89%

In₀.₅₃Ga₀.₄₇As/InAs Composite Channel MOS-HEMT Exhibiting 511 GHz f_τ and 256 GHz f _max

Markman

Brunelli

Goswami

et al. 2020

IEEE J. Electron Devices Soc.

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“…The presented work is based on two variations of a 20-nm gate-length InGaAs MOSHEMT technology [3]. The electrons are confined in an In 0.8 Ga 0.2 As channel with an In 0.52 Al 0.48 As barrier layer toward the substrate.…”

Section: -Nm Ingaas Moshemt Technologymentioning

confidence: 99%

“…Directly on top of the InGaAs channel, a bi-layer Al 2 O 3 /HfO 2 gate dielectric is deposited by atomic layer deposition. A detailed description of the MOSHEMT process is given in [3].…”

Section: -Nm Ingaas Moshemt Technologymentioning

confidence: 99%

“…In [3], we demonstrated a 20-nm gate-length MOSHEMT technology that reduces gate-leakage currents for an on-state bias by six orders of magnitude (<10 nA/mm) compared to our conventional 20-nm gate-length Schottky-contact HEMT technology. Still, short-channel effects, such as drain-induced barrier lowering, are major challenges since the electron confinement of the 2DEG is limited for conventional back barriers.…”

Section: Introductionmentioning

confidence: 98%

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InGaAs MOSHEMT W-Band LNAs on Silicon and Gallium Arsenide Substrates

Thome

Heinz

Leuther

2020

IEEE Microw. Wireless Compon. Lett.

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This letter presents the design, performance, and analysis of four low-noise amplifier (LNA) monolithic microwave integrated circuits (MMICs) operating in W-band. Two LNA designs were fabricated in two variations of a 20-nm gate-length metal-oxide-semiconductor high-electronmobility transistor (MOSHEMT) technology each. While for the first technology version the heterostructure is directly grown on the final gallium arsenide (GaAs) wafer, the second version uses direct wafer bonding to transfer the III-V heterostructure after the epitaxial growth to a silicon (Si) substrate. Based on the measured noise figure (NF) of the four MMICs over a comprehensive set of bias conditions, the impact of short-channel effects on the RF performance and possible improvements are analyzed. The first LNA covers an octave bandwidth with more than 15 dB of gain and an average NF (75-105 GHz) of 3.5 dB on a Si substrate. At 80 GHz, the second amplifier exhibits minimal NFs of 2.3 and 2.5 dB on GaAs and Si substrates, respectively. Compared to previously reported MOS-or Si-based technologies, the presented LNAs demonstrate state-of-the-art noise performance emphasizing the importance of electron confinement for highly scaled transistor technologies.

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“…N. Waldron et al [6] developed the aspect-ratio-trapping technique for heterogeneous integration, but the consistency and defects of the materials are difficult to manage. Recently, wafer bonding technology has been widely used to realize the integration of InGaAs channel material on Si substrates [7][8][9][10]. Compared with the aforementioned technology, wafer bonding can more easily form a high-quality InGaAs channel layer.…”

Section: Introductionmentioning

confidence: 99%

High-Performance InGaAs HEMTs on Si Substrates for RF Applications

et al. 2022

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In this paper, we have fabricated InGaAs high-electron-mobility transistors (HEMTs) on Si substrates. The InAlAs/InGaAs heterostructures were initially grown on InP substrates by molecular beam epitaxy (MBE), and the adhesive wafer bonding technique was employed to bond the InP substrates to Si substrates, thereby forming high-quality InGaAs channel on Si. The 120 nm gate length device shows a maximum drain current (ID,max) of 569 mA/mm, and the maximum extrinsic transconductance (gm,max) of 1112 mS/mm. The current gain cutoff frequency (fT) is as high as 273 GHz and the maximum oscillation frequency (fMAX) reaches 290 GHz. To the best of our knowledge, the gm,max and the fT of our device are the highest ever reported in InGaAs channel HEMTs on Si substrates at given gate length above 100 nm.

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20-nm In_0.8Ga_0.2As MOSHEMT MMIC Technology on Silicon

Cited by 28 publications

References 11 publications

In₀.₅₃Ga₀.₄₇As/InAs Composite Channel MOS-HEMT Exhibiting 511 GHz f_τ and 256 GHz f _max

In₀.₅₃Ga₀.₄₇As/InAs Composite Channel MOS-HEMT Exhibiting 511 GHz f_τ and 256 GHz f _max

InGaAs MOSHEMT W-Band LNAs on Silicon and Gallium Arsenide Substrates

High-Performance InGaAs HEMTs on Si Substrates for RF Applications

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20-nm In0.8Ga0.2As MOSHEMT MMIC Technology on Silicon

Cited by 28 publications

References 11 publications

In₀.₅₃Ga₀.₄₇As/InAs Composite Channel MOS-HEMT Exhibiting 511 GHz fτ and 256 GHz f max

In₀.₅₃Ga₀.₄₇As/InAs Composite Channel MOS-HEMT Exhibiting 511 GHz fτ and 256 GHz f max

InGaAs MOSHEMT W-Band LNAs on Silicon and Gallium Arsenide Substrates

High-Performance InGaAs HEMTs on Si Substrates for RF Applications

Contact Info

Product

Resources

About

20-nm In_0.8Ga_0.2As MOSHEMT MMIC Technology on Silicon

In₀.₅₃Ga₀.₄₇As/InAs Composite Channel MOS-HEMT Exhibiting 511 GHz f_τ and 256 GHz f _max

In₀.₅₃Ga₀.₄₇As/InAs Composite Channel MOS-HEMT Exhibiting 511 GHz f_τ and 256 GHz f _max