20.3 A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4<sup>th</sup>-Order Noise-Shaping SAR ADC

Lü, Jie; Zheng, Boyi; Flynn, Michael P.

doi:10.1109/isscc.2019.8662313

Cited by 19 publications

(4 citation statements)

References 3 publications

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“…The first conversion is for the redundancy, and the fine conversion adopts noise-shaping for higher resolution. Even without noise-shaping during the coarse conversion, the whole ADC can show a noise transfer function (NTF) that is same as that of the fine conversion if the midway update method based on redundancy [6] is used. Therefore, a loop filter is necessary only for the fine conversion and passive integration in [7], provided that the first-order NTF of (1) is adopted to enable noise-shaping without the use of a power-hungry amplifier or a multi-input comparator.…”

Section: Fine Sar Conversionmentioning

confidence: 99%

Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC

Kim

Chae

2021

Electronics

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A 2-then-1-bit/cycle noise-shaping successive-approximation register (SAR) analog-to-digital converter (ADC) for high sampling rate and high resolution is presented. The conversion consists of two phases of a coarse 2-bit/cycle SAR conversion for high speed and a fine 1-bit/cycle noise-shaping SAR conversion for high accuracy. The coarse conversion is performed by both voltage and time comparison for low power consumption. A redundancy after the coarse conversion corrects the error caused by a jitter noise during the time comparison. Additionally, a mismatch error between signal and reference paths is eliminated with the help of a tail-current-sharing comparator. The proposed ADC was designed in a 28 nm CMOS process, and the simulation result shows a 68.2 dB signal-to-noise distortion (SNDR) for a sampling rate of 480 MS/s and a bandwidth of 60 MHz with good energy efficiency.

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Section: Fine Sar Conversionmentioning

confidence: 99%

Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC

Kim

Chae

2021

Electronics

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“…Continuous-Time Delta-Sigma Modulator (CT∆ΣM) ADCs have also been reported for wide-band A/D conversion [47], but some key points such as the analog nature of the filter loop, the excess loop delay, and the clock jitter increase the complexity design especially with narrow processes nodes. Noise-Shaping SAR (NS-SAR) structures combined with time-interleaving techniques remove the need for analog circuits, relaxing technology scaling requirements and enabling high-bandwidth conversion with lower power consumption [48], [49].…”

Section: A/d Conversion Techniquesmentioning

confidence: 99%

VCO-ADCs with a Quadrature Band-Pass Noise-Transfer-Function

Gutierrez

Alvero-Gonzalez

Hernández

et al. 2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

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I would like to extend my sincere thanks to all the people who contributed to complete this academic work.First and foremost, I would like to express my deepest gratitude to my PhD advisor, Eric Gutierrez. I could not have undertaken this journey and written this thesis without his invaluable supervision, persistent support and patience. I am extremely thankful for his wise guidance and overall insights in this field that have helped me to grow intellectually. He has been my mentor, teacher, and the best advisor for my PhD degree.Thanks to the members of the Electronic Technology Department at Carlos III University of Madrid, who awarded me one of the full scholarships to study the Master in Electronic Systems Engineering, which gives me access to this doctoral program.I would like to offer my special thanks to Prof. Luis Hernández for give me the opportunity to join his research group. His treasured support allows me to conduct this thesis. I am also grateful to Prof. Susana Patón for her appreciation and encouragement who generously provided knowledge and expertise.Thanks to HiSilicon Sponsorship Program for MPW Prototyping for the funding and support provided in the implementation of the 65-nm test chip.I would like to thank all my colleagues of the microelectronics team, especially my lab mates, Andrés, Carlos y Pablo, for their kind help and cherished time spent together that have made this journey a wonderful time.Quiero agradecer a mi familia, la de sangre y la "postiza", y a mis amigos por su apoyo incondicional; ellos son mi arma espiritual. Mi agradecimiento imperecedero a mis padres, por todo el amor, la fuerza y la confianza que siempre me han transmitido. A pesar de la distancia, ellos han recorrido este camino conmigo. Agradezco inmensamente a mi hermana porque siempre me ha ayudado y me ha soportado sin importar lo difícil que haya podido ser; su presencia es una de mis mayores fortunas.El más grande de mis agradecimientos es para mi pareja, Harold, el mejor acompañante que he podido tener en esta travesía. Este trabajo es también resultado de su paciencia inquebrantable. Sus palabras han sido siempre mi mejor cura. Nunca sabré definir acertadamente la forma única que tienes de impulsarme. Espero ser capaz de concederte todo lo que me has entregado incondicionalmente. v

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“…The noise shaping technique has been actively investigated to address the challenge [ 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 ]. This technique moves the in-band quantization noise from the signal band to out-of-band for improved signal-to-noise ratio (SNR).…”

Section: Introductionmentioning

confidence: 99%

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

Choi

Lee

2022

Sensors

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Herein, we present a noise shaping successive-approximation-register (SAR) analog-to-digital converter (ADC) with an embedded passive gain multiplication technique. The noise shaping moves the in-band quantization noise from the signal band to out-of-band for improved signal-to-noise ratio (SNR). The proposed approach tackles the drawback of the previous active noise shaping (increased power and extra noise) and passive noise shaping (limited noise suppression and signal loss). Both noise shaping and gain multiplication are realized on-chip in an energy-efficient manner without an opamp. This approach uses only capacitors and switches in the finite impulse response (FIR) and infinite impulse response (IIR) filters. A comparator suppressing kickback noise is presented to handle the tradeoff between noise suppression and the filter capacitor size. The energy-efficient merged-capacitor switching (MCS) technique is effectively combined with rail-to-rail swing comparator and thermometer-coded capacitor array, which reduces the settling error in the digital to analog converter (DAC). The process-induced mismatch effect in the capacitive DAC is investigated using a behavioral model of the ADC. Additionally, we propose dynamic element matching (DEM) for the thermometer-coded capacitor array. The ADC is fabricated using a 0.18 μm CMOS process in an area of 0.26 mm2. Consuming 4.1 μW, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 66.5 dB and a spurious-free dynamic range (SFDR) of 79.1 dB. The figure-of-merit (FoM) of the ADC is 11.8 fJ/conversion-step.

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20.3 A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4^th-Order Noise-Shaping SAR ADC

Cited by 19 publications

References 3 publications

Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC

Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC

VCO-ADCs with a Quadrature Band-Pass Noise-Transfer-Function

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

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20.3 A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4th-Order Noise-Shaping SAR ADC

Cited by 19 publications

References 3 publications

Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC

Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC

VCO-ADCs with a Quadrature Band-Pass Noise-Transfer-Function

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

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Product

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20.3 A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4^th-Order Noise-Shaping SAR ADC