A 1.4V 60MHz Embedded Flash EEPROM has been de veloped, using a word-line booster circuit, a current comparing sense amplifier and an interleave architecture. A new worcL1ine booster circuit whch consists of a high performance charge pump, a voltage regulator and a voltage switch has supplied a stable voltage to the wordline decoder from the supply voltage of 1.4V. A clock-synchronizedread operation with an interleave architecture has contributed to doubling the maximum operating f q e n c y in the flash EEPROM.