2.5D/3D TSV processes development and assembly/packaging technology

Yoon, Seung Wook; Na, Duk Ju; Choi, Wooseok; Kang, Keon Taek; Yong, Chang Bum; Kim, Young Chul; Marimuthu, Pandi C.

doi:10.1109/eptc.2011.6184441

Cited by 11 publications

(3 citation statements)

References 3 publications

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“…Introduction A typical 2.5D interposer package consists of one or multiple guest dies stacked on top of a thinned TSV interposer, which is in turn assembled on either an organic flip chip BGA (FCBGA) or a ceramic substrate. [75][76][77][78][79] Figure 33 shows an example of a 2.5D interposer package. The two guest chips could be assembled side-by-side on the interposer as shown in the schematics or be replaced by one or more stacks of multiple dies (for example, memory cube).…”

Section: 5d Tsi Assembly Challengesmentioning

confidence: 99%

Heterogeneous 2.5D integration on through silicon interposer

Zhang¹,

Lin²,

Wickramanayaka³

et al. 2015

Applied Physics Reviews

125

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Section: 5d Tsi Assembly Challengesmentioning

confidence: 99%

Heterogeneous 2.5D integration on through silicon interposer

Zhang¹,

Lin²,

Wickramanayaka³

et al. 2015

Applied Physics Reviews

125

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“…It follows that heterogeneous integration is possible with the use of passive interposers. Although certain issues regarding the fabrication of TSVs, namely interposer thinning and known good silicon interposer (KGSi), associated with passive TSV interposers are similar to those observed in Active die fabricated with TSVs, their level of criticality is lower than that of the active die with TSVs [12]. Alternatives to the TSV Si interposer, organic interposers using Cu vias or glass interposers using Cu vias (TGV: Through Glass Vias) are also being researched in parallel.…”

Section: 5d Integration and Its High Power And High Temperature Appmentioning

confidence: 99%

The application of through silicon vias (or TSVs) for high power and temperature devices

Ranade

Havens

Srihari

2014

Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)

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Miniaturization and higher functionality have been and continue to be serious pursuits of the electronics industry. In relation to the miniaturization of package size, the 3D integration of devices using through silicon vias (or TSVs) is currently being researched extensively. 2.5D integration with a passive interposer is currently being researched as a step toward achieving the goal of complete 3D integration. This paper analyzes the packaging industry's transition from 2D to 3D integration of packages. Literature focused on manufacturability, materials of interest, geometrical dimensions, market trends, and customer focus is discussed in detail. The utilization of TSV packages in high power and high temperature products is the research area still to be explored. Hence, existing simulation data is extrapolated to high power die dimensions to analyze the effect of package dimensions on the thermo-mechanical behavior of TSV power die. Furthermore, a basic thermo-mechanical model of a Cufilled TSV passive interposer is studied under high power and high temperature field conditions. Multiple cases are simulated to study the effect of TSV dimensions and material properties on the thermo-mechanical behavior of power packages. The current limitations of TSVs in high power application s ar e stated based on th e r esults.KEY WORDS TSV, 2.5D and 3D integration, thermomechanical analysis, high power and high temperature application.

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“…Three-dimensional (3D) wafer-level packaging technology has the great potential to realize smaller size, lower fabrication cost, and high yield [1,2,3] by exploiting wafer bonding with a lid wafer containing vertical electrical feedthroughs. In particular, the vertical feedthrough interconnect technology has been intensively studied owing to its advantages of high integration levels with a small form factor [4], fast speed, and low power consumption due to reduced signal path [5,6], allowing 3D heterogeneous integration [7] for better functionality and process compatibility [3,8]. The fabrication of through wafer vias with high aspect ratio and via filling technologies is the critical process to realize vertical electrical interconnect, which has two important technologies including through silicon via (TSV) and through glass via (TGV).…”

Section: Introductionmentioning

confidence: 99%

Research on the Protrusions Near Silicon-Glass Interface during Cavity Fabrication

Zhang

Yang

et al. 2019

Micromachines

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Taking advantage of good hermeticity, tiny parasitic capacitance, batch mode fabrication, and compatibility with multiple bonding techniques, the glass-silicon composite substrate manufactured by the glass reflow process has great potential to achieve 3D wafer-level packaging for high performance. However, the difference in etching characteristics between silicon and glass inevitably leads to the formation of the undesired micro-protrusions near the silicon-glass interface when preparing a shallow cavity etched around a few microns in the composite substrate. The micro-protrusions have a comparable height with the depth of the cavity, which increases the risks of damages to sensitive structures and may even trigger electrical breakdown, resulting in thorough device failure. In this paper, we studied the characteristics of the chemical composition and etching mechanisms at the interface carefully and proposed the corresponding optimized solutions that utilized plasma accumulation at the interface to accelerate etching and bridge the gap in etching rates between different chemical compositions. Finally, a smooth transition of 131.1 nm was achieved at the interface, obtaining an ideal etching cavity surface and experimentally demonstrating the feasibility of our proposal. The micromachining solution is beneficial for improving the yield and structural design flexibility of higher performance micro-electromechanical systems (MEMS) devices.

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2.5D/3D TSV processes development and assembly/packaging technology

Cited by 11 publications

References 3 publications

Heterogeneous 2.5D integration on through silicon interposer

Heterogeneous 2.5D integration on through silicon interposer

The application of through silicon vias (or TSVs) for high power and temperature devices

Research on the Protrusions Near Silicon-Glass Interface during Cavity Fabrication

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