Polymers have found wide usage in microelectronics industry. Their moisture absorption properties cause the concern of reliability without hermeticity (RwoH). For printed circuit packages, the lamination process, the components assembly, and the field performance of final product are strongly influenced by the presence of high level moisture content. For instance, moisture is an important factor in the development of internal shorts through metal migration when printed circuit package is in service. Moisture can also cause dimensional changes in printed circuit cores and delamination during the soldering processes in components assembly, resulting in manufacturing yield loss and defects. Understanding moisture properties of resins and the resin glass composites are therefore important in developing a strategy to control the moisture content of final products. This paper will discuss the moisture fundamental properties of two resins and their resin glass systems. These properties will be related to their assembly and reliability performance.
Today’s consumer market demands electronics that are smaller, faster, and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer level chip scale package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence, the emphasis of reliability is shifting toward the study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and the bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the printed circuit board (PCB) by solder balls. The size of these solder balls is typically large enough (300 μm pre-reflow for 0.5-mm pitch and 250 μm pre-reflow for 0.4-mm pitch) to avoid the use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different silver (Ag) contents, backside lamination with different thicknesses, WLCSP type—direct and redistribution layer (RDL), bond pad thickness, and sputtered versus electroplated under bump metallurgy (UBM) deposition methods for 8 × 8, 9 × 9, and 10 × 10 array sizes. The test vehicles built using these design parameters were drop tested using Joint Electron Devices Engineering Council (JEDEC) recommended test boards and conditions as per JESD22-B11. Cross-sectional analysis was used to identify, confirm, and segregate the intermetallic and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data were collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and ungrouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.
Today’s consumer market demands electronics that are smaller, faster and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer Level Chip Scale Package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence the emphasis of reliability is shifting towards study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the PCB by solder balls. The size of these solder balls is typically large enough (300μm pre-reflow for 0.5mm pitch and 250μm pre-reflow for 0.4mm pitch) to avoid use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different Silver (Ag) content, backside lamination with different thickness, WLCSP type –Direct and Re-Distribution Layer (RDL), bond pad thickness, and sputtered versus electroplated Under Bump Metallurgy (UBM) deposition methods for 8×8, 9×9, and 10×10 array sizes. The test vehicles built using these design parameters were drop tested using JEDEC recommended test boards and conditions as per JESD22-B11. Cross sectional analysis was used to identify, confirm, and classify the intermetallic, and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data was collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and un-grouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.
System-On-Film (SOF) module is a complex integration of a fine pitch high density die and surface mounted discrete devices on a polyimide (PI) film laminate. The die is connected to the film using a thermo-compression flip-chip bonding (TCB) process which is capable of providing a very high density interconnect at less than 50um pitch. Several design and bonding parameters have to be controlled in order to achieve a reliable bond between the Au bumps on the die and the Sn plated Cu traces on the PI film. In the current work, the TCB process is studied using Finite Element Analysis (FEA) to optimize the design parameters and assure proper process margins. The resultant forces acting on the bump-to-trace interfaces are quantified across the different potential geometrical combinations. Baseline simulations showed higher stresses on specific bump locations and stress gradients acting on the bumps along the different sides of the die. These observations were correlated to both the failures and near failures on the actual test vehicles. Further simulations were then utilized to optimize and navigate design tradeoffs at both the die and flexible substrate design levels for a more robust design solution. Construction analysis performed on parts built using optimized design parameters showed significant improvements and correlated well with the simulation results.
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