Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages

Abstract

Today’s consumer market demands electronics that are smaller, faster, and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer level chip scale package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence, the emphasis of reliability is shifting toward the study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and the bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the printed circuit board (PCB) by solder balls. The size of these solder balls is typically large enough (300 μm pre-reflow for 0.5-mm pitch and 250 μm pre-reflow for 0.4-mm pitch) to avoid the use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different silver (Ag) contents, backside lamination with different thicknesses, WLCSP type—direct and redistribution layer (RDL), bond pad thickness, and sputtered versus electroplated under bump metallurgy (UBM) deposition methods for 8 × 8, 9 × 9, and 10 × 10 array sizes. The test vehicles built using these design parameters were drop tested using Joint Electron Devices Engineering Council (JEDEC) recommended test boards and conditions as per JESD22-B11. Cross-sectional analysis was used to identify, confirm, and segregate the intermetallic and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data were collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and ungrouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

Polymeric reinforcement approaches and materials selection to improve board-level drop reliability of SnAgCu soldered area array packages

“…The dominant failure mode was observed to be brittle fracture at the CSP IMC/solder interface for all the test groups except underfilled samples. The findings were similar to that reported by other studies [26][27][28]. The Fig.…”

Numerical Study on the Influence of Polyimide Thickness and Curing Temperature on Wafer Bow in Wafer Level Packaging

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