1Gsearch/sec Ternary Content Addressable Memory compiler with silicon-aware Early-Predict Late-Correct single-ended sensing

Arsovski, Igor; Hebig, Travis; Dobson, Daniel; Wistort, Reid

doi:10.1109/vlsic.2012.6243817

Cited by 10 publications

(4 citation statements)

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“…A dual ML TCAM is proposed to reduce the active ML capacitance [23]. Other techniques include adding a capacitor in each ML to limit the number of charges per search transaction [20], injecting a small current to each ML prior to the sensing phase [24], exploiting the input data pattern to reduce the ML segment switching probability [25], using a self-reference sense amplifier to stop the ML charging around the threshold voltage of the output inverter [26], and uneven injection of current in missed row versus matched row [27]. Shutting down redundant comparisons using pipelining [28], automated background checking [29], and precomputationbased CAM [30] to limit the number of searches have also been proposed to lower the power consumption.…”

Section: ) Energymentioning

confidence: 99%

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories

Karam

Puri

Ghosh³

et al. 2015

Proc. IEEE

170

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Section: ) Energymentioning

confidence: 99%

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories

Karam

Puri

Ghosh³

et al. 2015

Proc. IEEE

170

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“…To minimize the amount of leakage, we deployed high- [14]. (b) ML stability scheme [15] (c) Butterfly ML scheme [17]. devices in the 6T SRAM part.…”

Section: Multi-cam Cell For Leakage Reduction and Search Speed Ementioning

confidence: 99%

0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance

Tuan

Yin

Velayudhan

et al. 2014

IEEE J. Solid-State Circuits

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This work reports a fully parallel match-line (ML) structure with an automated background checking (ABC) scheme. MLs are pre-charged to an intermediate level by a pulsed current source to minimize power. The proposed ABC scheme uses two dummy rows for digitally adjusting the pulse width and the delay of the sense amplifier enable signals of the CAM without disturbing the normal operation. Therefore, it can continuously track the optimum ML swing, making the CAM tolerant to variations. The proposed ABC scheme achieves the power reduction of 5.5× compared with the conventional ML sensing scheme. In addition, multi-V t transistors are used in the CAM cell to reduce the leakage by 15× while improving the ML discharging speed by 2× when compared with the standard-V t devices at 1.2 V, 80°C. A test chip was prototyped using a standard 65 nm CMOS process. The average energy consumption is 0.77 fJ/bit/search at 1.2 V/500 MHz. Index Terms-CAM, match-line, small match line swing, variation tolerant design.

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“…If contradictory results are noticed between the two segments, then, late correction scheme is employed. In [9], the low swing of mismatching MLs reduces power. Reference [10] dynamically adds a dummy row to pull the precharge signal as soon as the match is detected, reducing the swing level of the mismatching MLs.…”

Section: Introductionmentioning

confidence: 99%

Content Addressable Memory—Early Predict and Terminate Precharge of Match-Line

Zackriya

Kittur

2017

IEEE Trans. VLSI Syst.

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A novel content addressable memory (CAM) architecture with a simple but very effective precharge controller is presented. CAM is a hardware search mechanism that precharges all its match lines (MLs) during the precharge phase, and a search is performed during the evaluate phase. With unique words stored in a CAM, all the MLs except the one, which matches with the search word have to be discharged for every search cycle. The MLs that mismatch will anyway drain the charge during the evaluation phase, here, those mismatching MLs are predicted early during the precharge phase to terminate the full precharging of such lines. This promises CAM with reduced power as well as improved search speed.Index Terms-Content addressable memory (CAM), dynamic precharging, high-speed search, precharge controller, shortcircuit current. 1063-8210

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1Gsearch/sec Ternary Content Addressable Memory compiler with silicon-aware Early-Predict Late-Correct single-ended sensing

Cited by 10 publications

References 0 publications

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories

0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance

Content Addressable Memory—Early Predict and Terminate Precharge of Match-Line

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