19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC

Sai, Akihide; Kondo, Satoshi; Ta, Tuan Thanh; Okuni, Hidenori; Furuta, Mamoru; Itakura, Tetsuro

doi:10.1109/isscc.2016.7418044

Cited by 4 publications

(3 citation statements)

References 6 publications

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“…In this way, the TDC gives a negligible contribution to the overall time resolution. The adoption of TDCs in an All-Digital PLL (ADPLL) to replace the analogue phase detectors has stimulated vigorous studies in the domain of ultrahigh resolution TDCs and several converters with ps grade resolution have been reported [50,51]. The research is now gearing towards TDCs with sub-ps resolution.…”

Section: Highly Integrated Low Noise Low Power Consumption and Ultraf...mentioning

confidence: 99%

Design considerations for a new generation of SiPMs with unprecedented timing resolution

Enoch¹,

Gola²,

Lecoq³

et al. 2021

J. Inst.

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The potential of photon detectors to achieve precise timing information is of increasing importance in many domains, PET and CT scanners in medical imaging and particle physics detectors, amongst others. The goal to increase by an order of magnitude the sensitivity of PET scanners and to deliver, via time-of-flight (TOF), true space points for each event, as well as the constraints set by future particle accelerators require a further leap in time resolution of scintillator-based ionizing radiation detectors, reaching eventually a few picoseconds resolution for sub MeV energy deposits. In spite of the impressive progress made in the last decade by several manufacturers, the Single Photon Time Resolution (SPTR) of SiPMs is still in the range of 70–120 ps FWHM, whereas a value of 10 ps or even less would be desirable. Such a step requires a break with traditional methods and the development of novel technologies. The possibility of combining the extraordinary potential of nanophotonics with new approaches offered by modern microelectronics and 3D electronic integration opens novel perspectives for the development of a new generation of metamaterial-based SiPMs with unprecedented photodetection efficiency and timing resolution.

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Section: Highly Integrated Low Noise Low Power Consumption and Ultraf...mentioning

confidence: 99%

Design considerations for a new generation of SiPMs with unprecedented timing resolution

Enoch¹,

Gola²,

Lecoq³

et al. 2021

J. Inst.

View full text Add to dashboard Cite

show abstract

“…The larger D in Z −D is, the worse stability will be at wider BW. In [24], a latency of nearly 3T REF limits its maximum BW to around 4 MHz at 50-MHz reference clock (CLK). In conventional study [25], the DLF is separated into two paths: the proportional path (K P path) and the integral path (K I path) without digital summing at the DLF output.…”

Section: B Wide Loop-bandwidth Fractional-n Dpllmentioning

confidence: 99%

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

Liu

Sun

Tang

et al. 2018

IEEE J. Solid-State Circuits

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This paper presents a Bluetooth low-energy (BLE) transceiver (TRX) achieving ultra-low-power operation for Internet-of-Things (IoT) applications. The proposed TRX utilizes a wide-bandwidth low-power fractional-N digital phase-locked loop (DPLL) as a central component to perform multiple roles: a direct frequency modulator for the transmitter (TX), an analogto-digital converter (ADC) for the receiver (RX), a local oscillator for RX, and a frequency and phase synchronizer for the RX. The DPLL-based single-path downconversion method is adapted to halve the analog baseband circuit to further reduce the power consumption while maintaining a high interference rejection. A DPLL-based ADC with a digital-to-analog converter feedback greatly improves the ADC dynamic range, which improves the RX sensitivity and interference tolerance. By maximally reducing the required radio frequency and analog front-end components in RX, an RX power consumption of 2.3 mW is achieved with a −94 dBm sensitivity. The RX also satisfied all interference requirements with a certain margin. A 5.0-mW TX is achieved when delivering an output power of 0 dBm with a frequency-shift keying error of only 1.89%.

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“…The vernier TDCs [14], [15] can achieve the sub-gate resolution but they suffer from large mismatchs between the fast and slow paths, and that requires a non-trivial calibration for each delay stage. The ADC-based TDCs can provide the desired resolution with reasonable linearity [16], [17]. However, the covered delay range is limited.…”

Section: Introductionmentioning

confidence: 99%

Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS

Chen

Yin

Zhang

et al. 2022

IEEE Trans. Circuits Syst. I

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Nonlinearity of a digital-to-time converter (DTC) is pivotal to spur performance in DTC-based all-digital phaselocked-loops (ADPLL). In this paper, we characterize and analyze the mismatch of cascaded-delay-unit DTCs. Through an improved built-in-self-test (BIST) time-to-digital converter (TDC) assisted with phase-to-frequency detector (PFD), a measurement system of sub-half-ps accuracy is constructed to conduct the characterization. Fabricated in 28-nm CMOS, the DTC transfer functions are measured, and mismatches are compared against Monte-Carlo simulation results. The integral nonlinearity (INL) results are compared against each other and converted to the in-band fractional spur level when the DTC would be deployed in the ADPLL. The BIST-TDC system thus characterizes the on-chip delays without expensive equipment or complex setup. The effectiveness of adding a PFD into the loop is validated. The entire BIST system consumes 0.6 mW with a system self-calibration algorithm to tackle the analog blocks' nonlinearities.

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19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC

Cited by 4 publications

References 6 publications

Design considerations for a new generation of SiPMs with unprecedented timing resolution

Design considerations for a new generation of SiPMs with unprecedented timing resolution

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS

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