17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time

Abstract

Many big-data (BD) processors reduce power consumption by employing ternary content-addressable-memory (TCAM) [1-2] with pre-stored signature patterns as filters to reduce the amount of data sent for processing in the following stage (i.e., wireless transmission). To further reduce standby power, BD-processors commonly use nonvolatile memory (NVM) to back up the signature patterns of SRAM-based TCAM (sTCAM) [3] during power interruptions or frequent-off operations. However, this 2-macro (sTCAM + NVM) scheme suffers long delays and requires considerable energy for wake-up operations, due to the word-by-word serial transfer of data between NVM and TCAM macros. Most of the signature patterns are seldom updated (written); therefore, single-macro nonvolatile TCAM (nvTCAM) can be used for BDprocessors to reduce area and facilitate fast/low-power wake-up operations, compared to the 2-macro approach. Previous nvTCAMs were designed using diode-connected 4T2R with STT-MTJ (D4T2R) [4], 2T2R with PCM [5], and 4T2R with ReRAM [2]; however, they suffer the following issues: (1) large cell area (A) and high write energy (E W ) due to the use of two NVM (2R) devices;(2) limited word-length (WDL, k-bits) caused by small current-ratio (I-ratio=I ML-MIS I(k×l ML-M )) between match-line (ML) mismatch current (I ML-MIS ) and ML leakage current of k matched cells (k×I ML-M ); (3) Long search delays (T SD ) and excessive search energy (E S ) due to large ML parasitic load (C ML ) and small I-ratio. ReRAM is promising for nvTCAM due to its low E W , high resistance-ratio (R-ratio), and multiple-level cell (MLC) capability. To overcome issue (1) to (3), this study develops an MLC-based 3T1R nvTCAM with bi-directional voltage-divider control (BVDC). A 2×64×64b 3T1R nvTCAM macro is fabricated using back-end-of-line (BEOL) ReRAM [6] and a 90nm CMOS process, with 2.27× cell size reduction as compared with sTCAM using the same technology and the T SD (=0.96ns) for WDL=64b.978-1-4799-6224-2/15/$31.00 ©2015 IEEE

Emerging Memory Technologies: Recent Trends and Prospects

“…The use of RRAM as ternary content-addressable-memory for fast-searching big data has been reported [70]. Adding RRAM cells on top of the SRAM cell enables the instant-on and instantoff power gating by storing data from SRAM to RRAM locally before going to standby mode, which saves the latency and power to transfer the data to off-chip or embedded flash, as shown in Figure 7.…”

Approximate Computing Using Multiple-Access Single-Charge Associative Memory

“…Several previous works have used NVMs to design stable and efficient TCAMs [15], [22], [21], [23]. Li et al [15] designed a 1Mb energy efficient 2T-2R TCAM which is 10X smaller than SRAM-based TCAM.…”

“…Li et al [15] designed a 1Mb energy efficient 2T-2R TCAM which is 10X smaller than SRAM-based TCAM. Another 3T-1R TCAM structure has been introduced in [22], which can search the entire CAM array in less than 1ns with very low energy consumption. An efficient 2Kb 4T-2MTJ based TCAM cell is proposed in [23].…”

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories

“…Other emerging technologies such as phase-change memory (PCM) [48], carbon nanotube field-effect transistors (CNTFETs) [49], [50], multigate transistor technologies such as FinFET, as well as single electron transistors have also been envisioned for CAM realization [51], [52]. Table 3 presents the quantitative comparison of the nano-CAMs in terms of area, speed, energy, and endurance [53]. It can be noted that ReRAM CAM can achieve better density, energy, and delay compared …”